2.1 DS Clarification: Nonvolatile Memory (NVM) Control

Section 13.2 incorrectly states the writing access for User IDs. The corrected Section 13.2 is shown below with changes highlighted in bold:

13.2.2 Writing Access

Only the User IDs and CONFIG words have write access enabled. The user can write to these blocks by setting the REG bits to 'b01 or 'b11. The WREN bit in NVMCON1 must be set to enable writes. This prevents accidental writes to the CONFIG words due to errant (unexpected) code execution. The WREN bit should be kept clear at all times, except when updating the CONFIG words. The WREN bit is not cleared by hardware. The WR bit will be inhibited from being set unless the WREN bit is set.

13.2.2.1 Writing to User IDs

The user needs to load the TBLPTR and TABLAT registers with the address and data byte respectively. Writing to the User IDs does not include an implicit erase cycle like the EEPROM/CONFIG words; hence, the user needs to clear the memory location pointed by TBLPTR, first by setting the FREE bit and executing the write command. An unlock sequence is required before setting the writing command. A single User ID byte is cleared at once (set to 0xFF). CPU execution is stalled and, at the completion of the write cycle, the WR bit is cleared in hardware and the NVM Interrupt Flag bit (NVMIF) is set and the CPU resumes operation.

Once the User ID byte is cleared, the user can now write the new value to that location. To do this, the user needs to execute the TBLWT instruction, followed by executing the write command. An unlock sequence is required before setting the write command. A single User ID byte is written at once. CPU execution is stalled and, at the completion of the write cycle, the WR bit is cleared in hardware and the NVM Interrupt Flag bit (NVMIF) is set. The new User ID value takes effect when the CPU resumes operation.

During the above operations, if TBLPTR points to an invalid address location (see Table 13-1), the WR bit is cleared without any effect and WRERR is set.