1.2.2 Accumulate Mode

In Accumulate mode, each new conversion is added to the ADC Accumulator Register trio (ADACCU:ADACCH:ADACCL) in addition to the ADRES register pair. A threshold comparison is performed on each new sample, and may set the ADTIF interrupt flag.

After each conversion, the result is added to the Accumulator, the threshold test is performed, and the ADC Count Register (ADCNT) is increased by one. The ADCNT register holds the number of conversion results that have been added to the Accumulator, up to a count of 255. It is important to note that ADCNT does not roll over, and any additional accumulation past 255 counts will not be tracked, although the Accumulator will still add new conversion results until the Accumulator overflows.

If an overflow occurs (in any computation mode except Basic mode), the ADC Accumulator Overflow (AOV) bit of the ADSTAT register will be set. The ADC Accumulator Clear Command (ACLR) of the ADCON2 register is used to clear the Accumulator, ADCNT, and the AOV bit. When ACLR = 1, the Accumulator, ADCNT, and the AOV bit are all cleared, but when using the ADCRC, this process may take a few instruction cycles to complete. When complete, hardware automatically clears ACLR.

The accumulated value can be right-shifted (divided) via the ADC Accumulated Calculation Right Shift Selection (CRS<2:0>) bits of the ADCON2 register. These bits allow the accumulated results to be right-shifted by the value of CRS (see Equation 1-3). The right-shifted result is stored in the ADC Filter Register pair (ADFLTRH:ADFLTRL), and is updated every conversion (see Table 1-2). It is important to note that if the right-shifted accumulator value exceeds the capacity of ADFLTR, or if the threshold computation overflows, the AOV bit will be set.