10.1 MCKRDY flag error
When PMC_CPU_CKR.MDIV is greater than 1, if the PMC_CPU_CKR.CSS field is modified, the MCKRDY signal may be stuck at 0.
Work Around
Use a software timeout of 64 cycles of CPU clock instead of polling the MCKRDY bit.
Affected Silicon Revisions
| A0 | A1 | A1-D1G | A1-D2G | ||||
| X | X | X | X |