13.1 Spurious DMA descriptor writing

Due to AXI transaction reordering, DMA descriptors writing may occur before the last image is written in the memory, even if the DONE flag is set. The user cannot read the DMA descriptors before the full image is written.

Work Around

  1. Poll the bit ISC_INTSR.DDONE.
  2. Perform an extra read of ISC_INTSR to enable DDR Controller writing.
  3. Poll the bit UDDRC_PSTAT.WR_PORT_BUSY_3 with:

    while (DDRUMCTL_REGS->UDDRC_PSTAT & UDDRC_PSTAT_WR_PORT_BUSY_3(1));

Once done, the full image is written in the memory and the DMA descriptors can be written.

Affected Silicon Revisions

A0A1A1-D1GA1-D2G
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