Features

The key features of blocks are:

• A block can be synthesized, simulated, and place-and-route the same way as a regular design.
• The place-and-route of the block can be locked to ensure repeatable performance.
• Performance, placement, and routing can be fixed absolutely; however these rules can be relaxed gradually, if necessary, to ensure that you can integrate the block into your top-level project.
• The block flow supports the following HDLs:
  • Verilog
  • VHDL
• The block flow supports SynplifyPro synthesis tool.
• Nested blocks (blocks instantiated inside other blocks) are supported. When publishing, only one file will be published that contains all the required information (including the nested block).