10.5.2 Trap Vector Details

Note: Any unimplemented or unused vector locations in the IVT should be programmed with the address of a default interrupt handler routine that contains a RESET instruction.

Table 10-2. Trap Vector Details
Vector Source	MPLAB^® XC-DSC Trap ISR Name	IRQ #	VECNUM	IVT Offset	Interrupt Bit Location
Vector Source	MPLAB^® XC-DSC Trap ISR Name	IRQ #	VECNUM	IVT Offset	Flag	Enable	Priority
Bus error - CPU X data bus error	_BusErrorTrap	N/A	2	0x8	INTCON3[0]	—	14
Bus error - CPU Y data bus error	_BusErrorTrap	N/A	2	0x8	INTCON3[1]	—	14
Bus error - DMA bus error	_BusErrorTrap	N/A	2	0x8	INTCON3[2]	—	14
Bus error - CPU instruction data bus error	_BusErrorTrap	N/A	2	0x8	INTCON3[3]	—	14
Illegal instruction	_IllegalInstructionTrap	N/A	3	0xC	INTCON1[2]	—	13
Address error	_AddressErrorTrap	N/A	4	0x10	INTCON1[3]	—	12
Stack error	_StackErrorTrap	N/A	5	0x14	INTCON1[4]	—	11
Math error - Divide by Zero	_MathErrorTrap	N/A	6	0x18	INTCON4[0]	—	10
Math error - Accumulator Shift error	_MathErrorTrap	N/A	6	0x18	INTCON4[1]	—	10
Math error - Accumulator B Catastrophic Overflow	_MathErrorTrap	N/A	6	0x18	INTCON4[2]	INTCON4[19]	10
Math error - Accumulator A Catastrophic Overflow	_MathErrorTrap	N/A	6	0x18	INTCON4[3]	INTCON4[19]	10
Math error - Accumulator B Overflow	_MathErrorTrap	N/A	6	0x18	INTCON4[4]	INTCON4[20]	10
Math error - Accumulator A Overflow	_MathErrorTrap	N/A	6	0x18	INTCON4[5]	INTCON4[21]	10
General error - DMT event trap	_GeneralTrap	N/A	7	0x1C	INTCON5[0]	—	9
General error - WDT Run event trap	_GeneralTrap	N/A	7	0x1C	INTCON5[1]	—	9
General error - XRAM PWB DED error	_GeneralTrap	N/A	7	0x1C	INTCON5[2]	—	9
General error - YRAM PWB DED error	_GeneralTrap	N/A	7	0x1C	INTCON5[3]	—	9
General error - soft trap	_GeneralTrap	N/A	7	0x1C	INTCON5[31]	—	9

dsPIC33AK256MPS306 Family Data Sheet

10.5.2 Trap Vector Details