43.15 Configurable Logic Block (CLB) Graphs

Figure 43-104. Single BLE Propagation Delay vs V_DD	Figure 43-105. I_DD vs V_DD (CLB Circuit Utilization > 50%, Asynchronous Design, No CLB Clock Frequency)
Figure 43-106. I_DD vs V_DD (CLB Circuit Utilization > 50%, Synchronous Design, Fixed CLB Input Switching)

DS40002664C

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