10.5 New Silicon Features and Enhancements

Libero SoC v2021.2 adds information about Power Up To Functional timing (PUFT) data in the Design Initialization Data and Memories report. To indicate the completion of initialization of each block (PCIe, XCVR, and RAM), a signal is asserted as part of device initialization after power-up. For example, the PCIE_INIT_DONE signal is asserted after all the PCIe-related registers are configured. The DEVICE_INIT_DONE signal from PF_INIT_MONITOR is the last signal asserted.

For more details, see the PolarFire FPGA and PolarFire SoC FPGA Device Power-Up and Resets User Guide.

Libero SoC v2021.2 introduces a distinct I/O standard called LVDS18G to support LVDS I/Os on GPIO banks with VDDI set to 1.8V.

Libero SoC v2021.2 adds an option to enable user control of the output clock port (HS_CLK) pattern on the PF_IOD_GENERIC_TX interface.

For more information, see the PolarFire FPGA and PolarFire SoC FPGA User I/O User Guide.

Libero SoC v2021.2 adds the capability of self-refresh entry and exit to LPDDR3.

For more details, see the PolarFire FPGA and PolarFire SoC FPGA Memory Controller User Guide.

Libero SoC v2021.2 adds an option to Export DOFF_N Port and enables fast simulation with the latest version of PF_QDR.

For more details, see the PolarFire FPGA and PolarFire SoC FPGA Memory Controller User Guide.

Libero SoC v2021.2 adds the following capabilities to SPI Flash programming.

• Support for loading STAGE3 initialization client when adding SPI Bitstream client in SPI Flash. Support for exporting STAGE3 file along with SPI bitstream file in the Export Bitstream dialog box.

• Support for loading binary image (.bin) SPI Flash clients.
• Programming support of Gigabit SPI Flash devices: GD25S512 and GD25Q256.
• Programming support of Micron MT25QL02G SPI Flash device.
• Programming support of Winbond W25Q128JWYIQ SPI Flash device.

For more information, see the Libero SoC Design Flow User Guide .

The PolarFire XCVR can source three different clocks into the fabric:

• TX_CLK
• RX_CLK
• REFCLK (FAB_REF_CLK)

These clocks contain high-frequency jitter that is not automatically considered by Libero in the timing report and SmartTime. It is recommended that users add clock-uncertainty constraints to these clocks in their design. The following table shows recommended values for clock uncertainty per clock, resource, and speed-grade.

set_clock_uncertainty -setup 0.150 [ get_pins { PF_XCVR_ERM_LANE2/I_XCVR/LANE0/TX_CLK_R } ]
 
set_clock_uncertainty -setup 0.175 [ get_pins { PF_XCVR_ERM_LANE2/I_XCVR/LANE0/RX_CLK_R } ]
 

The following example shows a clock-uncertainty constraint with STD speed grade.

# TX_CLK and RX_CLK on Globals
 
set_clock_uncertainty -setup 0.300 [ get_pins { PF_XCVR_ERM_LANE2/I_XCVR/LANE0/TX_CLK_G } ]
 
set_clock_uncertainty -setup 0.325 [ get_pins { PF_XCVR_ERM_LANE2/I_XCVR/LANE0/RX_CLK_G } ]
 
# FAB_REF_CLK on Global
 
set_clock_uncertainty -setup 0.275 [get_clocks PF_DDR4_C0_0/CCC_0/pll_inst_0/OUT1]

The automatic management of these constraints will be added in a future release of Libero SoC.

Libero SoC v2021.2 extends the PolarFire SoC standalone MSS configurator with the following enhancements:

• An option to have both SD and eMMC I/Os pre-configured if dynamic reconfiguration is needed by the application
• Package pin information for RefClk, DDR and SGMII I/Os added to the MSS configurator report
• An option to have the eMMC and CAN clock sourced from the fabric (production devices only).

For more information, see the Standalone MSS Configurator User Guide for PolarFire SoC

Libero SoC v2021.2 adds the ability to generate design-specific IBIS models for RTPF500T/TS/TL/TLS devices.

Libero SoC v2021.2 adds a diagnostic table of recommended pin assignments to guide you out of Dynamic CCC placement failures in RTG4, SmartFusion2, and IGLOO2 designs.

For more details, see the UG0586 - RTG4 FPGA Clocking ResourcesFPGA Clocking Resources User Guide.

Libero SoC v2021.2 adds the ability to securely update/rotate keys in Secure Production Programming Solution (SPPS) flows for SmartFusion2 and IGLOO2 devices.

For more details, see the Job Manager User Guide .