6.2 Changes that Address Important Issues

Libero SoC v2022.3 includes changes that address certain important issues.

6.2.1 PolarFire, RT PolarFire, and PolarFire SoC

6.2.1.1 Designs Containing TAMPER Core's PORDIGEST

As part of Microchip’s continuous improvement efforts, the PORDIGEST parameter for the TAMPER core has been updated to reflect correct settings for Fabric, sNVM, and security configurations for PolarFire families. In addition, for PolarFire SoC, the TAMPER core would have eNVM configuration. This means that the TAMPER core version will be different for PolarFire/RT PolarFire and PolarFire SOC families.

These changes ensure that the export bitstream has consistent settings. With this change any Libero designs with TAMPER core prior to v2002.3 will be invalidated, requiring you to regenerate Bitstream, Flash Pro Express, and Job Manager Data.

6.2.1.2 Designs Using PF_CCC IP Core

Libero SoC v2022.3 resolves an issue introduced in Libero SoC v2022.2 with PF_CCC v2.2.214. Designs where an existing instance of PF_CCC IP was upgraded to v2.2.214 incorrectly used a LOCK_CNT parameter value of 0x0 instead of 0x8. This incorrect parameter setting reduces the number of extra reference clock cycles to wait before asserting the PLL lock output, and could result in undesirable PLL lock output behavior. Upgrading to Libero SoC v2022.3 and PF_CCC core v2.2.220 resolves this issue.

For more information, see Microchip PCN MAAN-13RNNO081 at https://www.microchip.com/product-change-notifications/#/20073/MAAN-13RNNO081.

6.2.2 PolarFire

6.2.2.1 MPF050T/TS/TL/TLS Static Power

Updated static power for MPF050T/TS/TL/TLS based on data from silicon characterization.

6.2.3 PolarFire SoC

6.2.3.1 Improved Static Power for PolarFire SOC

For the PolarFire SoC device for 100C, 1.03V, MAX case conditions. Worst-case IDD static power values are updated for MPFS025T/TS/TL/TLS, MPF095T/TS/TL/TLS, MPFS160T/TS/TL/TLS, MPFS250T/TS/TL/TLS, and MPFS460T/TS/TL/TLS devices.

6.2.3.2 MPFS250T/TS/TL/TLS Sector Clock Delay

As part of Microchip’s continuous improvement efforts, Libero SoC v2022.3 has been updated to improve the accuracy of the MPFS250T/TS/TL/TLS sector clock model and data. During such efforts, Microchip found a design could have up to a 40 ps change in its MIN or MAX delay slack and uncover new violations. Therefore, Microchip recommends performing the actions described in the following sections.

New and Ongoing Designs

Microchip recommends upgrading to Libero SoC v2022.3 or later and re-running STA to ensure the updated timing data is used when performing STA.

Designs Completed Prior to Libero SoC v2022.3

No further actions are listed if the design successfully completed full system functional hardware testing on every production unit over the entire operating conditions range.
For completed designs that do not meet the criteria above, Microchip recommends opening the completed design in Libero SoC v2022.3 or later and running an incremental Timing Driven Place and Route (TDPR) with Minimum Delay Repair (MDR) enabled to see whether the violations can be resolved. If they cannot be resolved, run a full TDPR with MDR enabled.

6.2.4 SmartFusion2, IGLOO2

6.2.4.1 LSRAM Feed-through Write Delay

As part of Microchip’s continuous improvement efforts, Libero SoC v2022.3 has been updated to improve the accuracy of the LSRAM Feed-through write clock-to-out model and data, described in the following sections. During such efforts, Microchip found a design could have up to a 800 ps change in its MAX delay slack and uncover new violations. Therefore, Microchip recommends performing the actions described in the section below.

New and Ongoing Designs

Microchip recommends upgrading to Libero SoC v2022.3 or later and re-running STA to ensure the updated timing data is used when performing STA.

Designs Completed Prior to Libero SoC v2022.3

No further actions are listed if the design successfully completed full system functional hardware testing on every production unit over the entire operating conditions range.

For completed designs that do not meet the criteria above, Microchip recommends opening the completed design in Libero SoC v2022.3 or later and running an incremental Timing Driven Place and Route (TDPR) with Minimum Delay Repair (MDR) enabled to see whether the violations can be resolved. If they cannot be resolved, run a full TDPR with MDR enabled.

If the completed design cannot be opened in Libero SoC v2022.3, observe the following guidelines:
  • Designs that do not contain any LSRAM instance with the above configuration are not impacted.
  • Designs where the paths involving clock-to-out of all LSRAM instances with the above configuration have 800 ps margin are not impacted.
  • Insert a margin of 800 ps on paths that do not meet the above criteria through a max-delay constraint (that is, clock-period - 800 ps), and then rerun an incremental Timing Driven Place and Route (TDPR) with Minimum Delay Repair (MDR) enabled. If the violations cannot be resolved, run a full TDPR with MDR enabled.

6.2.5 RTG4

6.2.5.1 SDF Files Generated for Back-annotated Simulation

The SDF file generated for back-annotated simulation of RTG4 designs was updated to be consistent with SmartTime (Verify Timing report) for the following cases:
  • Pin swapping on CCC cells
  • Bypassed internal I/O cells