4.7 Resolved Issues

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The following table lists the customer-reported defects and enhancement requests resolved in Libero SoC v2023.2 that have case numbers. Resolution of previously reported “Known Issues and Limitations” are also noted in this table.

Table 4-3. Customer-reported Defects and Enhancement Requests with Case Numbers
Case Number	Summary	Resolution
01305388	MPF050T/TS/TL/TLS, MPFS025T/TS/TL/TLS: High-speed I/O clock connectivity update.	See section MPF050T/TS/TL/TLS, MPFS025T/TS/TL/TLS: High-Speed I/O Clock Connectivity Update.
493642-2616127596, 00935635, 01275935	PolarFire MPF200T FCVG484: I/O Bank 4 and 5 VDDI DRC.	See section PolarFire MPF200T FCVG484: I/O Banks 4 and 5 VDDI DRC, Design Invalidation.
01241342	USB library access on Linux prevents the support of multiple eFP6 programmers with Libero/FlashPro Express and SmartDebug.	Added support for multiple eFP6 programmers on the Linux operating system.
01023769	Reported issue for generic package instantiation.	Resolved the issue for generic package instantiation.
01255870	Prior to Libero SoC v2023.2, designs targeting PolarFire MPF050T/TS/TL/TLS FPGAs and MPFS025T/TS/TL/TLS SoC could have placed High-Speed I/O Bank Clock (HS_IO_CLK) instances at locations that are not routable.	See section MPF050T/TS/TL/TLS, MPFS025T/TS/TL/TLS: High-Speed I/O Clock Connectivity Update.
01134983	Programmable I/O delay update on ports using combined I/O registers.	See section Programmable I/O Delay Update on Ports Using Combined I/O Registers.
01150189	PF_CCC: PLL solver accuracy.	See section PF_CCC: Improved PLL Solver Accuracy.
01204463	PF_IOD_OCTAL_DDR: Non-blocking assignments encountered in combinational block.	PF_IOD_OCTAL_DDR core has been updated to address a limiting issue, with no functional change.
00896987	PF_IOD: OCTAL_PHY differential DQS.	See section PF_IOD: OCTAL_PHY Update.
01254298	PF_SOC: MSS: Need to add an ADD/CMD offset in the MSS configurator for DDR3/LPDDR3 and DDR4/LPDDR4.	Added an ADD/CMD offset in the PolarFire SoC MSS configurator for DDR3/LPDDR3 and DDR4/LPDDR4.
493642-2843645269	SerDes REFCLK pin configuration details.	See section Generate FPGA Array Data - Init Config Report: Add SERDES REFCLK I/O Settings.
01083419, 1094794	CoreFIR_PF core generation for the MPFS250T_ES device with a silver license.	CoreFIR_PF core generates properly for the MPFS250T_ES device with a silver license.
01269754	RTG4_SRAM_AHBL_AXI: Logic issue when two transactions occur consecutively, such that you read from a different slave using AHB, and subsequently attempt to write using this slave.	Resolved logic issue.
01265049	Support for ISSI IS25LP512M SPI-Flash device with FlashPro 6.	Support has been added for an ISSI IS25LP512M SPI-Flash device with FlashPro 6.
01302899	Encryption public keys and script availability.	See section Encryption Public Keys and Script.
01227224	Default TCK frequency for FlashPro 6 during Scan Chain.	Changed the default TCK frequency from 4MHz to 1MHz with FlashPro 6 during Scan Chain.
01278337	IBIS Term models supported for differential I/Os.	IBIS Term models supported for differential I/Os.
01284803	RTG4FCCCECALIB DEADLOCK: 50MHz RC Osc Output stuck when ARSTN exposed and GLx set to LOW until PLL locks.	See section RTG4 CCC Improvements.
01257768	Support for Macronix MX25L25645GSPI-Flash device with FlashPro 6.	Support has been added for a Macronix MX25L25645GSPI-Flash device with FlashPro 6.
01152975	The jitter report `place_and_route_jitter_report.txt` is being generated with Multipass Place and Route operations.	This issue has been resolved.
01236884	Ability to disable timing of GB cell.	Added support for wildcard in set_disable_timing.
01108897	PolarFire PCIe FTS, L0s acceptable latency, PL_TXSWING values are not reflecting in the design initialization report.	In the GUI, the fast training sequence (FTS) and TXSWING options are set to default values and cannot be changed by users.
01236650	Power estimation for the E51 Monitoring core was missing from the Power Estimator spreadsheet.	This issue has been resolved.
01211657	Simulation issue with the PF_IOD_GENERIC_TX IP core's TX clock signal.	Fixed a TX clock simulation issue by assigning OE_DATA properly.
01285956	RTG4 IBIS sub models are not exported in the exported IBIS file.	RTG4 IBIS submodels for DDRIO conditions have been updated.
493642-2663302704	SmartDebug could not debug design when a non-Microchip device is connected in chain with Microchip device.	SmartDebug can be used to debug design when a non-Microchip device is connected in chain with Microchip device.

The following table lists the customer-reported defects and enhancement requests resolved in Libero SoC v2023.2 that do not have case numbers. Resolution of previously reported “Known Issues and Limitations” are also noted in this table.

Table 4-4. Customer-reported Defects and Enhancement Requests (No Case Numbers)
Summary	Resolution
Users cannot export a component description Tcl script for SmartDesign Testbench.	Added support for SmartDesign Testbench to export a component description Tcl script.
SmartDesign loses loopback connectivity of the instance when updating the instance port list.	This issue has been resolved: Instance loopback connections are now preserved when an instance port list changes.
Bus slices are lost when a new slice is created that overlaps existing ones.	This issue has been resolved: Bus slices are now preserved when creating a new slice with an overlapping range.
Jitter reports should state that values are peak-to-peak.	Added a statement in the report header that values are peak-to-peak.
PolarFire IBIS Transceiver Reference clock models are not supported.	PolarFire IBIS Transceiver Reference clock models are now supported.
The tool crashes when checking constraints when a master clock is invalid.	Added a check to prevent such crashes.
Creating or opening a FlashPro Express project should not require hardware to be connected.	This issue has been resolved: A FlashPro Express job project can now be created or opened without requiring a connected programmer.
Clarify voptargs required for QuestaSim Pro ME simulation.	Added a QuestaSim Pro ME note in the Libero SoC Simulation Library Setup Instructions about design optimization during simulation. To access this document, go to Pre-Compiled Simulation Libraries, and then click the link for the Libero SoC Design Suite Simulation Library Setup Instructions document.
When min-delay slack is from worst corner, the tap delay inserted on max-delay timing is determined by the min-delay slack.	Best practices recommend that you avoid max-delay timing violation when performing min-delay repair.