2.8.1 Hardwired Clocks

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The Hardwired Clock (HCLK) is a low-skew network that can directly drive the clock inputs of all sequential modules (R-cells, I/O registers, and embedded RAM/FIFOs) in the device with no antifuse in the path. All four HCLKs are available everywhere on the chip.

Timing Characteristics

The following tables lists the dedicated (hardwired) array clock networks of Axcelerator devices.

Table 2-74. AX125 Dedicated (Hardwired) Array Clock Networks Worst-Case Commercial Conditions VCCA = 1.425V, VCCI = 3.0V, T_J = 70 °C
Parameter	Description	–2 Speed		–1 Speed		Std Speed		Units
Parameter	Description	Min.	Max.	Min.	Max.	Min.	Max.	Units
Dedicated (Hardwired) Array Clock Networks
t_HCKL	Input low to high	—	3.02	—	3.44	—	4.05	ns
t_HCKH	Input high to low	—	3.03	—	3.46	—	4.06	ns
t_HPWH	Minimum pulse width high	0.58	—	0.65	—	0.77	—	ns
t_HPWL	Minimum pulse width low	0.52	—	0.59	—	0.69	—	ns
t_HCKSW	Maximum skew	—	0.06	—	0.07	—	0.08	ns
t_HP	Minimum period	1.15	—	1.31	—	1.54	—	ns
t_HMAX	maximum frequency	—	870	—	763	—	649	MHz

Table 2-75. AX250 Dedicated (Hardwired) Array Clock Networks Worst-Case Commercial Conditions VCCA = 1.425V, VCCI = 3.0V, T_J = 70 °C
Parameter	Description	–2 Speed		–1 Speed		Std Speed		Units
Parameter	Description	Min.	Max.	Min.	Max.	Min.	Max.	Units
Dedicated (Hardwired) Array Clock Networks
t_HCKL	Input low to high	—	2.57	—	2.93	—	3.45	ns
t_HCKH	Input high to low	—	2.61	—	2.97	—	3.50	ns
t_HPWH	Minimum pulse width high	0.58	—	0.65	—	0.77	—	ns
t_HPWL	Minimum pulse width low	0.52	—	0.59	—	0.69	—	ns
t_HCKSW	Maximum skew	—	0.06	—	0.07	—	0.08	ns
t_HP	Minimum period	1.15	—	1.31	—	1.54	—	ns
t_HMAX	maximum frequency	—	870	—	763	—	649	MHz

Table 2-76. AX500 Dedicated (Hardwired) Array Clock Networks Worst-Case Commercial Conditions VCCA = 1.425V, VCCI = 3.0V, T_J = 70 °C
Parameter	Description	–2 Speed		–1 Speed		Std Speed		Units
Parameter	Description	Min.	Max.	Min.	Max.	Min.	Max.	Units
Dedicated (Hardwired) Array Clock Networks
t_HCKL	Input low to high	—	2.35	—	2.68	—	3.15	ns
t_HCKH	Input high to low	—	2.44	—	2.79	—	3.27	ns
t_HPWH	Minimum pulse width high	0.58	—	0.65	—	0.77	—	ns
t_HPWL	Minimum pulse width low	0.52	—	0.59	—	0.69	—	ns
t_HCKSW	Maximum skew	—	0.06	—	0.07	—	0.08	ns
t_HP	Minimum period	1.15	—	1.31	—	1.54	—	ns
t_HMAX	maximum frequency	—	870	—	763	—	649	MHz

Table 2-77. AX1000 Dedicated (Hardwired) Array Clock Networks Worst-Case Commercial Conditions VCCA = 1.425V, VCCI = 3.0V, T_J = 70 °C
Parameter	Description	–2 Speed		–1 Speed		Std Speed		Units
Parameter	Description	Min.	Max.	Min.	Max.	Min.	Max.	Units
Dedicated (Hardwired) Array Clock Networks
t_HCKL	Input low to high	—	3.02	—	3.44	—	4.05	ns
t_HCKH	Input high to low	—	3.03	—	3.46	—	4.06	ns
t_HPWH	Minimum pulse width high	0.58	—	0.65	—	0.77	—	ns
t_HPWL	Minimum pulse width low	0.52	—	0.59	—	0.69	—	ns
t_HCKSW	Maximum skew	—	0.06	—	0.07	—	0.08	ns
t_HP	Minimum period	1.15	—	1.31	—	1.54	—	ns
t_HMAX	maximum frequency	—	870	—	763	—	649	MHz

Table 2-78. AX2000 Dedicated (Hardwired) Array Clock Networks Worst-Case Commercial Conditions VCCA = 1.425V, VCCI = 3.0V, T_J = 70 °C
Parameter	Description	–2 Speed		–1 Speed		Std Speed		Units
Parameter	Description	Min.	Max.	Min.	Max.	Min.	Max.	Units
Dedicated (Hardwired) Array Clock Networks
t_HCKL	Input low to high	—	3.02	—	3.44	—	4.05	ns
t_HCKH	Input high to low	—	3.03	—	3.46	—	4.06	ns
t_HPWH	Minimum pulse width high	0.58	—	0.65	—	0.77	—	ns
t_HPWL	Minimum pulse width low	0.52	—	0.59	—	0.69	—	ns
t_HCKSW	Maximum skew	—	0.06	—	0.07	—	0.08	ns
t_HP	Minimum period	1.15	—	1.31	—	1.54	—	ns
t_HMAX	Maximum frequency	—	870	—	763	—	649	MHz