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Axcelerator Family FPGAs Datasheet
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Introduction
1
Benefits
2
Specifications
3
Features
4
Ordering Information
5
Device Resources
6
Axcelerator Family Device Status
7
Temperature Grade Offerings
8
Speed Grade and Temperature Grade Matrix
9
Packaging Data
1
General Description
1.1
Device Architecture
1.2
Design Environment
1.3
Summary
1.4
Related Documents
2
Electrical Specifications
2.1
Operating Conditions
2.2
Thermal Characteristics
2.3
I/O Specifications
2.4
Voltage-Referenced I/O Standards
2.5
Differential Standards
2.6
Module Specifications
2.7
Routing Specifications
2.8
Global Resources
2.9
Axcelerator Clock Management System
2.10
Embedded Memory
2.11
Other Architectural Features
2.12
Programming
3
Package Pin Assignments
3.1
BG729
3.2
FG256
3.3
FG324
3.4
FG484
3.5
FG676
3.6
FG896
3.7
FG1152
3.8
PQ208
3.9
CQ208
3.10
CQ256
3.11
CQ352
3.12
CG624
4
Revision History
Microchip FPGA Support
Microchip Information
Trademarks
Legal Notice
Microchip Devices Code Protection Feature
