1.2 Parameters

The following table contains the receiver lane margining parameters as defined in the PCIe Gen5 Specification and the corresponding values used in the NVMe 5016 design. It is recommended not to deviate from the following values.

Table 1-1. PCIe RX Lane Margining Parameters
Parameter Name	Description	NVMe 5016 Design		NVMe 5016 PCM FW Settings
Parameter Name	Description	Min	Max	Capacity Values
M_{NumTimingStep}	Number of time steps from default (to either left or right), range is ± 0.2 UI. Timing offset must increase monotonically. The number of steps in both positive (toward the end of the unit interval) and negative (toward the beginning of the unit interval) must be identical.	8	63	16 steps
M_{MaxTimingOffset}	Offset from default at maximum step value as percentage of a nominal UI at 16.0 GT/s. A zero value might be reported if the vendor chooses not to report the offset.	20%	50%	40% (0.40UI)
M_{NumVoltageSteps}	Number of voltage steps from default (either up or down), minimum range ± 50 mV as measured by 16.0 GT/s reference equalizer. Voltage offset must increase monotonically. The number of steps in both positive and negative direction from the default sample location must be identical. This value is undefined if M_{VoltageSupported} is 0b.	32	127	64 steps
M_{MaxVoltageOffset}	Offset from default at maximum step value as percentage of one volt. A zero value might be reported if the vendor chooses not to report the offset when M_{VoltageSupported} is 1b. This value is undefined if M_{VoltageSupported} is 0b.	5	50%	12% (120 mV)
M_{SamplingRateVoltage}	The ratio of bits tested to bits received during voltage margining. A value of zero is a ratio of 1:64 (1 bit of every 64 bits received), and a value of 63 is a ratio of 64:64 (all bits received).	0	63	31
M_{SamplingRateTiming}	The ratio of bits tested to bits received during voltage margining. A value of zero is a ratio of 1:64 (1 bit of every 64 bits received), and a value of 63 is a ratio of 64:64 (all bits received).	0	63	31
M_{VoltageSupported}	1b indicates that voltage margining is supported.	0	1	1
M_{IndLeftRightTiming}	1b indicates independent left or right timing margin supported.	0	1	1
M_{IndUpDownVoltage}	1b independent up and down voltage margining supported.	0	1	1
M_{IndErrorSampler}	1b margining does not produce errors (change in the error rate) in data stream (that is, the error sampler is independent) 0b margining might produce errors in the data stream.	0	1	1
M_MaxLanes	Maximum number of lanes minus one that can be margined at the same time. It is recommended that this value be greater than or equal to the number of lanes in the link minus one. Encoding behavior is undefined if software attempts to margin more than M_MaxLanes+1 at the same time.¹	0	Device dependent	Max Lanes -1 (3)
M_{SampleReportingMethod}	Indicates whether sampling rates (M_{SamplingRateVoltage} and M_{SamplingRateTiming}) are supported (1) or a sample count is supported (0). One of the two methods is supported by each device.	0	1	1
M_ErrorCount	If M_{IndErrorSampler} is 1b this is a count of the actual bit errors since margining started. If M_{IndErrorSampler} is 0b this is the actual count of the logical errors since margining started. The count saturates at 63.	0	Returned from measurement	Number of errors detected by current capture is reported as part of the Margin Step command results.
M_SampleCount	Value = 3*log2 (number of bits margined). Where number of bits margined is a count of the actual number of bits tested during margining. The count stops when margining stops. The count saturates at 127 (after approximately 5.54 × 10^12 bits). The count resets to zero when a new margin command is received.	0	Returned from measurement	Number of samples collected is modified to fit in the status register after a Report Sample Count command is issued (see description).
Note: 1. This value is permitted to exceed the number of lanes in the link minus one.