Introduction
The PIC18F26/46/56Q84 devices that you have received conform functionally to the current device data sheet (DS40002259D), except for the anomalies described in this document.
The silicon issues discussed in the following pages are for silicon revisions with the Device and Revision IDs listed in the table below.
The errata described in this document will be addressed in future revisions of the PIC18F26/46/56Q84 silicon.
Note: This document summarizes all silicon errata issues from
all revisions of silicon, previous as well as current.
| Part Number | Device ID | Revision ID | ||
|---|---|---|---|---|
| A1 | A2 | B0 | ||
| PIC18F26Q84 | 0xA300 | 0xA001 | 0xA002 | 0xA400 |
| PIC18F46Q84 | 0xA301 | 0xA001 | 0xA002 | 0xA400 |
| PIC18F56Q84 | 0xA302 | 0xA001 | 0xA002 | 0xA400 |
Important: Refer to the Device/Revision ID section in
the current “PIC18FXXQ84 Family Programming Specification” (DS40002137) for more
detailed information on Device Identification and Revision IDs for your specific
device.
| Module | Feature | Item No. | Issue Summary | Affected Revisions | ||
|---|---|---|---|---|---|---|
| A1 | A2 | B0 | ||||
| UTMR | Level-triggered ERS Start/Reset condition | Dead Zone Exists in Level-Triggered Start/Reset Condition When an ERS Signal Is Generated Due to an SFR Access | Dead zone exists in level-triggered Start/Reset condition when ERS signal is generated due to an SFR access | X | X | X |
| Hardware Reset condition | Reset Does Not Happen at Period Match When the Prescaler > 0 and the Timer Stops at Period Match | Reset does not happen at period match when the prescaler > 0 and the Timer stops at period match (includes One Shot mode) | X | X | X | |
| Output Pulse | 1.1.3 | Pulse output does not occur at period match when the prescaler = 1 | X | X | X | |
| Clear command | Clear Command May Not Work Properly in Asynchronous Mode | Clear command may not work properly | X | X | X | |
| Interrupts | Interrupts Do Not Work When Leaving Debug Mode | Interrupts do not work after the user exits a debug session | X | X | X | |
| I2C | Start and Stop interrupt function | The I2C Start and/or Stop Flags May Be Set When I2C Is Enabled | The I2C Start and/or Stop flags may be set when I2C is enabled | X | X | X |
| Clock Stretching | CSTR Bit Is Not Cleared after Bus Time-Out | CSTR bit will not clear after a bus time-out | X | X | X | |
| Bus free divider ratio | The Bus Free Divider Ratio BFREDR = 1 Value Is Not Functional | BFREDR =1 mode is nonfunctional | X | X | X | |
| Host data request | MDR Bit Is Not Cleared after Bus Time-Out | MDR bit will not clear after a bus time-out | X | X | X | |
| Clock stretching | Bus Time-Out Not Detected Properly When External Host Clock Stretches | Bus time-out not detected during clock stretching | X | X | X | |
| Clock stretching | Clock Stretch Disable Not Working Properly | Disabling clock stretching can fail with specific timing | X | X | X | |
| Multi-Host mode | Bus Collision Followed by a Stop Condition During a Transaction by an External Host Device May Hang the Bus | Bus collisions can hang the bus in mult-host mode | X | X | X | |
| Clock Stretching | Writing to the I2CCNT Register During Clock Stretching May Corrupt the I2CCNT Value | I2CCNT value may be corrupted if written to during clock stretching | X | X | X | |
| SMT | Reset bit | Reset Bit | SMT stops working if RST is set while the prescaler setting is not zero | X | X | X |
| ADCC with Context | Double sample conversions | An Unexpected Acquisition Time is Added Between the First and Second Conversions | An unexpected acquisition time is added between the first and second conversion | X | X | X |
| PIC18 Core | FSR shadow registers | FSR Shadow Registers Are Not Writable | FSR shadow registers are not writable | X | X | X |
| UART | Stop bit | UART TXDE Signal May Go Low Before the STOP Bit Has Been Entirely Transmitted | TXDE signal may go low before the Stop bit has been entirely transmitted | X | X | X |
| ICD | Single-Step (SSTEP) function | Single-Step Function Does Not Execute at SW Breakpoint | Single-Step function does not execute at Software Breakpoint | X | X | X |
| PWM | PWM mode | Wrong Duty Cycle for CCP Module | Wrong duty cycle for the CCP module | X | X | X |
| ICSP™ | Low-Voltage Programming (LVP) | Low-Voltage Programming Not Possible | LVP is not possible when VDD is below BORV while BOR is enabled | X | X | X |
| CAN FD | Masks/Filters | Filters 8–11 Will Erroneously Accept Incoming Messages With SID of 0x000 | Filters 8–11 will erroneously accept incoming messages with SID of 0x000 | X | X | |
| Instruction Set | PUSHL instruction | 1.11.1 | The PUSHL instruction executes
incorrectly | X | X | X |
| Timer 1 | Gate Interrupt | Changing the Timer1 Gate Source May Cause Unexpected Interrupts | Writing to the gate source select may set the gate interrupt flag | X | X | X |
| Memory | DIA | 1.13.1 | The TSLR2 and TSHR2 Values Stored in the DIA Table are Incorrect | X | X | X |
| Capture/Compare/PWM (CCP) | Compare Toggle Mode | 1.14.1 | CCP Compare Toggle Output Mode Does Not Work as Expected | X | X | X |
| Power-Saving Modes | XLP Power Mode | XLP Power Mode Does Not Work as Expected | XLP Power Mode Does Not Work as Expected | X | X | X |
|
Note: Only issues indicated in the last column
apply to the current silicon revision.
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