8 Assignment 6: MVIO - VDDIO2 Failure Detection
In this assignment, the AVR128DB48 Curiosity Nano will be configured to use two voltage domains VDD and VDDIO2. VDD is supplied by the CNANO voltage regulator, while VDDIO2 is supplied by OP0, which is configured as a voltage follower with the DAC as an input.
The Digital-to-Analog Converter (DAC) is configured to create the input voltage to OP0. The output from the DAC will therefore be the voltage level for VDDIO2.
The Analog-to-Digital Converter (ADC) is configured to sample VDDIO2 divided by 10. The measured VDDIO2 is streamed over to the MPLAB® Data Visualizer using the data streamer protocol.
When SW0 is pressed, the output from the DAC will be reduced, resulting in a VDDIO2 interrupt detecting the failure on the VDDIO2 line.
The starting point for this assignment is the Atmel Studio Solution Assignment6 found in Assignment6.
- Objectives
- Introduce an error to VDDIO2 by lowering the supply voltage bellow it’s specifications
- Understand how the AVR DB can detect that VDDIO2 falls bellow its minimum requirement
- Use the ADC to measure VDDIO2 using the internal connection
- Plot the measured VDDIO2 using the MPLAB® Data Visualizer