10.4.2 Configuration

Figure 10-1. Host-Client Relation High-Speed Bus Matrix, SAM C20/C21
  1. The AHB-APB bridge D is available only on SAM C20/C21 N.
  2. The CAN peripheral is available only on C21.
Table 10-5. Bus Matrix Hosts
Bus Matrix Hosts Host ID
CM0+ - Cortex M0+ Processor 0
DSU - Device Service Unit 1
DMAC - Direct Memory Access Controller / Data Access 2
Table 10-6. Bus Matrix Clients
Bus Matrix Clients Client ID
Internal Flash Memory 0
SRAM Port 4 - CM0+ Access 1
SRAM Port 6 - DSU Access 2
AHB-APB Bridge A 3
AHB-APB Bridge B 4
AHB-APB Bridge C 5
SRAM Port 5 - DMAC Data Access 6
DIVAS - Divide Accelerator 7
Table 10-7. SRAM Port Connections
SRAM Port Connection Port ID Connection Type
CM0+ - Cortex M0+ Processor 0 Bus Matrix
DSU - Device Service Unit 1 Bus Matrix
DMAC - Direct Memory Access Controller - Data Access 2 Bus Matrix
DMAC - Direct Memory Access Controller - Fetch Access 0 3 Direct
DMAC - Direct Memory Access Controller - Fetch Access 1 4 Direct
DMAC - Direct Memory Access Controller - Write-Back Access 0 5 Direct
DMAC - Direct Memory Access Controller - Write-Back Access 1 6 Direct
CAN0 - Controller Area Network 0 7 Direct
Reserved 8 Reserved
MTB - Micro Trace Buffer 9 Direct