10.4.3 SRAM Quality of Service
To ensure that Hosts with latency requirements get sufficient priority when accessing RAM, the different Hosts can be configured to have a given priority for different type of access.
The Quality of Service (QoS) level is independently selected for each Host accessing the RAM. For any access to the RAM, the RAM also receives the QoS level. The QoS levels and their corresponding bit values for the QoS level configuration is shown in below.
| Value | Name | Description |
|---|---|---|
| 0x0 | DISABLE | Background (no sensitive operation) |
| 0x1 | LOW | Sensitive Bandwidth |
| 0x2 | MEDIUM | Sensitive Latency |
| 0x3 | HIGH | Critical Latency |
If a Host is configured with QoS level DISABLE (0x0) or LOW (0x1), there will be minimum latency of one cycle for the RAM access.
The priority order for concurrent accesses are decided by two factors: first the QoS level for the Host and second a static priority as shown in the Table 10-7. The lowest port ID has the highest static priority.
The MTB has fixed QoS level HIGH (0x3) and the DSU has fixed QoS level LOW (0x1).
The CPU QoS level can be written/read at address 0x4100A114, bits [1:0]. Its reset value is 0x3. (The APBB.HMATRIXHS bit need to be set first.)
Refer to different Host QOSCTRL registers for configuring QoS for the other Hosts (for SAM C21: CAN, DMAC; for SAM C20: DMAC).