37.8.3 LUT Control x

Note: LUTCTRLn register is Enable Protected when CCL.LUTCTRLn.ENABLE = 1.
Name: LUTCTRLn
Offset: 0x08 + n*0x04 [n=0..3]
Reset: 0x00000000
Property: PAC Write-Protection, Enable-protected

Bit 3130292827262524 
 TRUTH[7:0] 
Access R/WR/WR/WR/WR/WR/WR/WR/W 
Reset 00000000 
Bit 2322212019181716 
  LUTEOLUTEIINVEIINSEL2[3:0] 
Access R/WR/WR/WR/WR/WR/WR/W 
Reset 0000000 
Bit 15141312111098 
 INSEL1[3:0]INSEL0[3:0] 
Access R/WR/WR/WR/WR/WR/WR/WR/W 
Reset 00000000 
Bit 76543210 
 EDGESEL FILTSEL[1:0]  ENABLE  
Access R/WR/WR/WR/W 
Reset 0000 

Bits 31:24 – TRUTH[7:0] Truth Table

These bits define the value of truth logic as a function of inputs IN[2:0].

Bit 22 – LUTEO LUT Event Output Enable

ValueDescription
0 LUT event output is disabled.
1 LUT event output is enabled.

Bit 21 – LUTEI LUT Event Input Enable

ValueDescription
0 LUT incoming event is disabled.
1 LUT incoming event is enabled.

Bit 20 – INVEI Inverted Event Input Enable

ValueDescription
0 Incoming event is not inverted.
1 Incoming event is inverted.

Bits 8:11, 12:15, 16:19 – INSELx LUT Input x Source Selection

These bits select the LUT input x source:

ValueNameDescription
0x0 MASK Masked input
0x1 FEEDBACK Feedback input source
0x2 LINK Linked LUT input source
0x3 EVENT Event input source
0x4 IO I/O pin input source
0x5 AC AC input source: CMP[0] (LUT0) / CMP[1] (LUT1)/ CMP[2] (LUT2) / CMP[3] (LUT3)
0x6 TC TC input source: TC0 (LUT0) / TC1 (LUT1)/ TC2 (LUT2) / TC3 (LUT3)
0x7 ALTTC Alternative TC input source: TC1 (LUT0) / TC2 (LUT1) / TC3 (LUT2) / TC4 (LUT3)
0x8 TCC TCC input source: TCC0 (LUT0) / TCC1 (LUT1) / TCC2 (LUT2) / TCC0 (LUT3)
0x9 SERCOM SERCOM input source: SERCOM0 (LUT0) / SERCOM1 (LUT1)/ SERCOM2 (LUT2) / SERCOM3 (LUT3)
0xA ALT2TC Second alternative TC input source: TC4 (LUT0) / TC5 (LUT1) / TC6 (LUT2) / TC7 (LUT3). Only available on SAM C20/C21 N variants.
0xB ASYNCEVENT Asynchronous event input source. Only available on SAM C20/C21 N variants.
0xC - 0xF Reserved Reserved

Bit 7 – EDGESEL Edge Selection

ValueDescription
0 Edge detector is disabled.
1 Edge detector is enabled.

Bits 5:4 – FILTSEL[1:0] Filter Selection

These bits select the LUT output filter options:

Filter Selection

ValueNameDescription
0x0 DISABLE Filter disabled
0x1 SYNCH Synchronizer enabled
0x2 FILTER Filter enabled
0x3 - Reserved

Bit 1 – ENABLE LUT Enable

ValueDescription
0 The LUT is disabled.
1 The LUT is enabled.