38.6.2.8 Conversion Timing and Sampling Rate

The following figure shows the ADC timing for a single conversion. A conversion starts after the software or event start are synchronized with the GCLK_ADCx clock. The input channel is sampled in the first half CLK_ADCx period.

Figure 38-3. ADC Timing for One Conversion in 12-bit Resolution

The sampling time can be increased by using the Sampling Time Length bit group in the Sampling Time Control register (SAMPCTRL.SAMPLEN). As example, the next figure is showing the timing conversion with sampling time increased to six CLK_ADC cycles.

Figure 38-4. ADC Timing for One Conversion with Increased Sampling Time, 12-bit

The ADC can also provide offset compensation, as shown in the following figure. The offset compensation is enabled by the Offset Compensation bit in the Sampling Control register (SAMPCTRL.OFFCOMP).

Note: ADC sampling time is fixed to 4 ADC Clock cycles when offset compensation (OFFCOMP =1) is used.

In free running mode, the sampling rate R_S is calculated by

R_S = f_{CLK_ADC} / ( n_SAMPLING + n_OFFCOMP + n_DATA)

Here, n_SAMPLING is the sampling duration in CLK_ADC cycles, n_OFFCOMP is the offset compensation duration in clock cycles, and n_DATA is the bit resolution. f_{CLK_ADC} is the ADC clock frequency from the internal prescaler: f_{CLK_ADC} = f_{GCLK_ADC} / 2^(1 + CTRLB.PRESCALER)

Figure 38-5. ADC Timing for One Conversion with Offset Compensation, 12-bit

The impact of resolution on the sampling rate is seen in the next two figures, where free-running sampling in 12-bit and 8-bit resolution are compared.

Figure 38-6. ADC Timing for Free Running in 12-bit Resolution

In free running mode, the sampling rate R_S is calculated by:

R_S = f_{CLK_ADC} / ( n_SAMPLING + n_OFFCOMP + n_DATA)

Where,

n_SAMPLING is the sampling duration in CLK_ADC cycles, n_OFFCOMP is the offset compensation duration in clock cycles, and n_DATA is the bit resolution. f_{CLK_ADC} is the ADC clock frequency from the internal prescaler: f_{CLK_ADC} = f_{GCLK_ADC} / 2^(1 + CTRLA.PRESCALER).

The propagation delay of an ADC measurement is given by:

PropagationDelay = \frac{1 + Resolution}{f_{ADC}}

Example. In order to obtain 1 MSPS in 12-bit resolution with a sampling time length of four CLK_ADC cycles, f_{CLK_ADC} must be 1 Msps * (4 + 12) = 16 MHz. As the minimal division factor of the prescaler is 2, GCLK_ADC must be 32 MHz.