25.8.19 Channel Control B

This register affects the DMA channel that is selected in the Channel ID register (CHID.ID).
Name: CHCTRLB
Offset: 0x44
Reset: 0x00000000
Property: PAC Write-Protection, Enable-Protected

Bit 3130292827262524 
       CMD[1:0] 
Access R/WR/W 
Reset 00 
Bit 2322212019181716 
 TRIGACT[1:0]       
Access R/WR/W 
Reset 00 
Bit 15141312111098 
   TRIGSRC[5:0] 
Access R/WR/WR/WR/WR/WR/W 
Reset 000000 
Bit 76543210 
  LVL[1:0]EVOEEVIEEVACT[2:0] 
Access R/WR/WR/WR/WR/WR/WR/W 
Reset 0000000 

Bits 23:22 – TRIGACT[1:0] Trigger Action

These bits define the trigger action used for a transfer.

TRIGACT[1:0] Name Description
0x0 BLOCK One trigger required for each block transfer
0x1 - Reserved
0x2 BEAT One trigger required for each beat transfer
0x3 TRANSACTION One trigger required for each transaction

Bits 13:8 – TRIGSRC[5:0] Trigger Source

These bits define the peripheral trigger which is source of the transfer. For details on trigger selection and trigger modes, refer to Transfer Triggers and Actions and CHCTRLB.TRIGACT.

Table 25-2. Peripheral Trigger Source
Value Name Description
0x00 DISABLE Only software/event triggers
0x01 TSENS TSENS Result Ready Trigger
0x02 SERCOM0 RX SERCOM0 RX Trigger
0x03 SERCOM0 TX SERCOM0TX Trigger
0x04 SERCOM1 RX SERCOM1 RX Trigger
0x05 SERCOM1 TX SERCOM1 TX Trigger
0x06 SERCOM2 RX SERCOM2 RX Trigger
0x07 SERCOM2 TX SERCOM2 TX Trigger
0x08 SERCOM3 RX SERCOM3 RX Trigger
0x09 SERCOM3 TX SERCOM3 TX Trigger
0x0A SERCOM4 RX SERCOM4 RX Trigger
0x0B SERCOM4 TX SERCOM4 TX Trigger
0x0C SERCOM5 RX SERCOM5 RX Trigger
0x0D SERCOM5 TX SERCOM5 TX Trigger
0x0E CAN0 DEBUG CAN0 Debug Trigger
0x0F CAN1 DEBUG CAN1 Debug Trigger
0x10 TCC0 OVF TCC0 Overflow Trigger
0x11 TCC0 MC0 TCC0 Match/Compare 0 Trigger
0x12 TCC0 MC1 TCC0 Match/Compare 1 Trigger
0x13 TCC0 MC2 TCC0 Match/Compare 2 Trigger
0x14 TCC0 MC3 TCC0 Match/Compare 3 Trigger
0x15 TCC1 OVF TCC1 Overflow Trigger
0x16 TCC1 MC0 TCC1 Match/Compare 0 Trigger
0x17 TCC1 MC1 TCC1 Match/Compare 1 Trigger
0x18 TCC2 OVF TCC2 Overflow Trigger
0x19 TCC2 MC0 TCC2 Match/Compare 0 Trigger
0x1A TCC2 MC1 TCC2 Match/Compare 1 Trigger
0x1B TC0 OVF TC0 Overflow Trigger
0x1C TC0 MC0 TC0 Match/Compare 0 Trigger
0x1D TC0 MC1 TC0 Match/Compare 1 Trigger
0x1E TC1 OVF TC1 Overflow Trigger
0x1F TC1 MC0 TC1 Match/Compare 0 Trigger
0x20 TC1 MC1 TC1 Match/Compare 1 Trigger
0x21 TC2 OVF TC2 Overflow Trigger
0x22 TC2 MC0 TC2 Match/Compare 0 Trigger
0x23 TC2 MC1 TC2 Match/Compare 1 Trigger
0x24 TC3 OVF TC3 Overflow Trigger
0x25 TC3 MC0 TC3 Match/Compare 0 Trigger
0x26 TC3 MC1 TC3 Match/Compare 1 Trigger
0x27 TC4 OVF TC4 Overflow Trigger
0x28 TC4 MC0 TC4 Match/Compare 0 Trigger
0x29 TC4 MC1 TC4 Match/Compare 1 Trigger
0x2A ADC0 RESRDY ADC0 Result Ready Trigger
0x2B ADC1 RESRDY ADC1 Result Ready Trigger
0x2C SDADC RESRDY SDADC Result Ready Trigger
0x2D DAC EMPTY DAC Empty Trigger
0x2E PTC EOC PTC End of Conversion Trigger
0x2F PTC WCOMP PTC Window Compare Trigger
0x30 PTC SEQ PTC Sequence Trigger
0x31 SERCOM6 RX SERCOM6 RX Trigger
0x32 SERCOM6 TX SERCOM6 TX Trigger
0x33 SERCOM7 RX SERCOM6 RX Trigger
0x34 SERCOM7 TX SERCOM6 TX Trigger
0x35 TC5 OVF TC5 Overflow Trigger
0x36 TC5 MC0 TC5 Match/Compare 0 Trigger
0x37 TC5 MC1 TC5 Match/Compare 1 Trigger
0x38 TC6 OVF TC6 Overflow Trigger
0x39 TC6 MC0 TC6 Match/Compare 0 Trigger
0x3A TC6 MC1 TC6 Match/Compare 1 Trigger
0x3B TC7 OVF TC7 Overflow Trigger
0x3C TC7 MC0 TC7 Match/Compare 0 Trigger
0x3D TC7 MC1 TC7 Match/Compare 1 Trigger

Bits 6:5 – LVL[1:0] Channel Arbitration Level

These bits define the arbitration level used for the DMA channel, where a high level has priority over a low level. For further details on arbitration schemes, refer to 25.6.2.4 Arbitration.

These bits are not enable-protected.

TRIGACT[1:0] Name Description
0x0 LVL0 Channel Priority Level 0
0x1 LVL1 Channel Priority Level 1
0x2 LVL2 Channel Priority Level 2
0x3 LVL3 Channel Priority Level 3

Bit 4 – EVOE Channel Event Output Enable

This bit indicates if the Channel event generation is enabled. The event will be generated for every condition defined in the descriptor Event Output Selection (BTCTRL.EVOSEL).

This bit is available only for the least significant DMA channels. Refer to table: User Multiplexer Selection and Event Generator Selection of the Event System for details.

ValueDescription
0 Channel event generation is disabled.
1 Channel event generation is enabled.

Bit 3 – EVIE Channel Event Input Enable

This bit is available only for the least significant DMA channels. Refer to table: User Multiplexer Selection and Event Generator Selection of the Event System for details.

ValueDescription
0 Channel event action will not be executed on any incoming event.
1 Channel event action will be executed on any incoming event.

Bits 2:0 – EVACT[2:0] Event Input Action

These bits define the event input action, as shown below. The action is executed only if the corresponding EVIE bit in CHCTRLB register of the channel is set.

These bits are available only for the least significant DMA channels. Refer to table: User Multiplexer Selection and Event Generator Selection of the Event System for details.

EVACT[2:0] Name Description
0x0 NOACT No action
0x1 TRIG Normal Transfer and Conditional Transfer on Strobe trigger
0x2 CTRIG Conditional transfer trigger
0x3 CBLOCK Conditional block transfer
0x4 SUSPEND Channel suspend operation
0x5 RESUME Channel resume operation
0x6 SSKIP Skip next block suspend action
0x7 - Reserved