9.2 Physical Memory Map

The High-Speed bus is implemented as a bus matrix. All High-Speed bus addresses are fixed, and they are never remapped in any way, even during boot. The 32-bit physical address space is mapped as follows:

Table 9-1. SAM C20/C21 Physical Memory Map(1)
Memory Start address Size Size Size Size
x18 x17 x16 x15
Embedded Flash 0x00000000 256 Kbytes 128 Kbytes 64 Kbytes 32 Kbytes
Embedded RWW section 0x00400000 8 Kbytes 4 Kbytes 2 Kbytes 1 Kbytes
Embedded high-speed SRAM 0x20000000 32 Kbytes 16 Kbytes 8 Kbytes 4 Kbytes
AHB-APB Bridge A 0x40000000 64 Kbytes 64 Kbytes 64 Kbytes 64 Kbytes
AHB-APB Bridge B 0x41000000 64 Kbytes 64 Kbytes 64 Kbytes 64 Kbytes
AHB-APB Bridge C 0x42000000 64 Kbytes 64 Kbytes 64 Kbytes 64 Kbytes
AHB-APB Bridge D 0x43000000 64 Kbytes - - -
AHB DIVAS 0x48000000 64 Kbytes 64 Kbytes 64 Kbytes 64 Kbytes
IOBUS 0x60000000 64 Kbytes 64 Kbytes 64 Kbytes 64 Kbytes

Note: 1. x = SAM C20/C21 G/J/E/N. The N-series (100-pin devices) does not include x16 and x15 option.

Table 9-2. SAM C20/C21 Flash Memory Parameters(1)
Device Flash size (FLASH_PM) Number of pages (FLASH_P) Page size (FLASH_W)
x18 256Kbytes 4096 64 bytes
x17 128Kbytes 2048 64 bytes
x16 64Kbytes 1024 64 bytes
x15 32Kbytes 512 64 bytes

Note: 1. x = SAM C20/C21 G/J/E/N. The N-series (100-pin devices) does not include x16 and x15 option.

Table 9-3. SAM C20/C21 RWW Section Parameters(1)
Device Flash size (FLASH_PM) Number of pages (FLASH_P) Page size (FLASH_W)
x18 8Kbytes 128 64 bytes
x17 4Kbytes 64 64 bytes
x16 2Kbytes 32 64 bytes
x15 1Kbytes 16 64 bytes

Note: 1. x = SAM C20/C21 G/J/E/N. The N-series (100-pin devices) does not include x16 and x15 option.