21.4.3.2 Frequency Correction

The RTC Frequency Correction functionality employs periodic counter corrections to compensate for an oscillator that is too slow or too fast. Frequency correction requires that the Prescaler bit field in the Control A register (CTRLA.PRESCALER) be configured to DIVn, where n > 1.

The digital correction circuit adds or subtracts cycles from the RTC prescaler to adjust the frequency in approximately 1 ppm (parts per million) steps. Digital correction is achieved by adding or skipping a single count in the prescaler once every 8,192 CLK_RTC_OSC cycles. The Correction Value bit field in the Frequency Correction register (FREQCORR.VALUE) determines the number of times the adjustment is applied over 128 of these periods. The resulting correction is as follows:

This results in a resolution of 0.95367 ppm.

The Correction Sign bit in the Frequency Correction register (FREQCORR.SIGN) determines the direction of the correction. A positive value will add counts and increase the period (reducing the frequency), while a negative value will reduce the counts per period (increasing the frequency).

Digital correction also affects the generation of periodic events from the prescaler. When the correction is applied at the end of the correction cycle period, the interval between the previous periodic event and the next occurrence may also be shortened or lengthened, depending on the correction value.