Multi-buffer or circular buffer modes by linking multiple descriptors
2 Channels:
Enable up to 2 independent transfers
Automatic descriptor fetch for each channel
Suspend/resume operation support for each channel
Flexible Arbitration Scheme:
4 configurable priority levels for each channel
Fixed or round-robin priority scheme within each priority level
Data Transfer from 1 KB to 256 KB in a Single Block Transfer
Multiple Addressing Modes:
Static
Configurable increment scheme
Optional Interrupt Generation:
On block transfer complete
On error detection
On channel suspend
2 Event Inputs:
One event input for each of the 2 lowest-numbered DMA channels
Can be configured to trigger normal, periodic, or conditional transfers
Can be configured to suspend or resume channel operation
2 Event Outputs:
One event output for each of the 2 lowest-numbered DMA channels
Can be configured to generate event output on beat, block, or transaction transfer completion
Error Management Supported by Write-Back Function:
Dedicated write-back memory section for each channel to store ongoing descriptor transfer
CRC Polynomial Options:
CRC-16 (CRC-CCITT)
CRC-32 (IEEE® 802.3)
The online versions of the documents are provided as a courtesy. Verify all content and data in the device’s PDF documentation found on the device product page.
