4.1.1 Cortex M0+ Configuration
| Features | PIC32CM6408PL10 Configuration |
|---|---|
| Interrupt lines | 16 |
| Data endianness | Little-endian |
| SysTick timer | Present |
| Number of watchpoint comparators | 1 |
| Number of breakpoint comparators | 4 |
| Halting debug support | Present |
| Multiplier | Fast (single cycle) |
| Single-cycle I/O port | Present |
| Wake-up interrupt controller | Not supported |
| Vector Table Offset Register | Present |
| Unprivileged/Privileged support | All accesses are privileged |
| Memory Protection Unit | None |
| Reset all registers | Absent |
| Instruction fetch width | 32-bit |
The Arm Cortex-M0+ core has the following bus interfaces:
- A single 32-bit AMBA-3 AHB-Lite system interface provides connections to peripherals and all system memory, including Flash and RAM
- A single 32-bit I/O port bus interfaces to the PORT with 1-cycle loads and stores