30.1 Features

  • Full-Duplex, Four-Wire Interface
  • One-Level Transmit Buffer, Two-Level Receive Buffer
  • Supports all Four SPI Modes of Operation
  • Single Data Direction Operation Allows Alternate Function on the MISO or MOSI Pin
  • Selectable LSb- or MSb-First Data Transfer
  • Can be used with DMA
  • Host Operation:
    • 8-bit Clock Generator
    • Hardware-controlled SS
  • Client Operation:
    • 8-bit Address Match Operation
    • Operation in all Sleep Modes
    • Wake on SS Transition