15.1 Features

  • Voltage Regulator System
    • Main voltage regulator: Low Dropout (LDO) in Active mode
    • Ultra Low-Power (ULP) voltage regulator in Standby sleep mode
  • Brown-out Detection Monitors the Power Supply to Prevent Operation Below a Programmable Level
    • Three modes:
      • Enabled (Continuous)
      • Sampled
      • Disabled
    • Separate selection of mode for active and sleep modes
    • Voltage Level Monitor (VLM) with interrupt
    • Programmable VLM level relative to the BOD level
  • MVIO System
    • Two mode configurations:
      • Dual Supply mode, with independent supply target voltage, ramp and removal on VDD and VDDIO2
      • Single Power Supply mode, with MVIO supply monitors are turned off to minimize current consumption
    • Mode selection fuse
    • Interrupt request for VDDIO2 power loss
    • CPU-readable VDDIO2 Power Status bit (domain-monitor status)
    • Pin access and port override function the same way as with VDD