23.4.1 Initialization

The following registers are enable-protected, meaning that they can only be written when the TCC is disabled(CTRLA.ENABLE=0):
  • Control A register (CTRLA), except for the Run Standby (RUNSTDBY), Enable (ENABLE) and Software Reset (SWRST) bits
  • Fault Control x register (FCTRLx)
  • Waveform Extension Control register (WEXCTRL)
  • Driver Control register (DRVCTRL)
  • Event Control register (EVCTRL)

Enable-protected bits in the CTRLA register can be written at the same time as CTRLA.ENABLE is written to '1', but not at the same time as CTRLA.ENABLE is written to '0'. Enable-protection is denoted by the “Enable-Protected” property in the register description.

Before the TCC is enabled, it must be configured as outlined by the following steps:
  1. Enable the TCC bus clock (CLK_TCCn_APB).
  2. If Capture mode is required, enable the channel in capture mode by writing a '1' to the Capture Enable bit in the Control A register (CTRLA.CPTEN).
Optionally, the following configurations can be set before enabling TCC:
  1. Select desired setting in the Prescaler bit field in the Control A register (CTRLA.PRESCALER).
  2. Select desired setting in the Prescaler and Counter Synchronization bit field in Control A register (CTRLA.PRESCSYNC).
  3. If down-counting operation is desired, write '1' to the Counter Direction bit in the Control B Set register (CTRLBSET.DIR) .
  4. Select the desired operation in the Waveform Generation bit field in the WAVE register (WAVE.WAVEGEN).
  5. Select the desired output polarity in the Waveform Output Polarity bit field in the WAVE register (WAVE.POL).
  6. The waveform output can be inverted for individual channels using the Waveform Output x Inversion bit in the Driver Control register (DRVCTRL.INVENx).