21.7.7 Synchronization Busy
| Name: | SYNCBUSY |
| Offset: | 0x10 |
| Reset: | 0x00000000 |
| Property: | – |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| COUNTSYNC | |||||||||
| Access | R | ||||||||
| Reset | 0 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| COMP1 | COMP0 | PER | COUNT | FREQCORR | ENABLE | SWRST | |||
| Access | R | R | R | R | R | R | R | ||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bit 15 – COUNTSYNC COUNT Read Resynchronization Enable Synchronization Busy
This bit is cleared when the synchronization of CTRLA.COUNTSYNC is complete.
This bit is set when the synchronization of CTRLA.COUNTSYNC is started.
Bits 5, 6 – COMPn Compare n Value Synchronization Busy
This bit is cleared when the synchronization of the COMP[n] register is complete.
This bit is set when the synchronization of the COMP[n] register is started.
Bit 4 – PER Counter Period Synchronization Busy
This bit is cleared when the synchronization of the PER register is complete.
This bit is set when the synchronization of the PER register is started.
Bit 3 – COUNT Counter Value Synchronization Busy
This bit is cleared when the synchronization of the COUNT register is complete.
This bit is set when the synchronization of the COUNT register is started.
Bit 2 – FREQCORR Frequency Correction Synchronization Busy
This bit is cleared when the synchronization of the FREQCORR register is complete.
This bit is set when the synchronization of the FREQCORR register is started.
Bit 1 – ENABLE Enable Synchronization Busy
This bit is cleared when the synchronization of CTRLA.ENABLE is complete.
This bit is set when the synchronization of CTRLA.ENABLE is started.
Bit 0 – SWRST Software Reset Synchronization Busy
This bit is cleared when the synchronization of CTRLA.SWRST is complete.
This bit is set when the synchronization of CTRLA.SWRST is started.