10.3 Block Diagram

Figure 10-1. Device Clocking Diagram

The generation of the Peripheral Clock signals (GCLK_PERIPH) and the Main Clock (GCLK_MAIN) can be seen in the following figure:

Figure 10-2. Device Clocking Diagram

Note: Generic Clock Generator 0 (GCLK_GEN0) is always the source of the GCLK_MAIN signal, and the default clock source is OSCHF divided by six, i.e. 4 MHz (after successful device initialization).