4.2.2 Interrupt Line Mapping
Each of the interrupt lines is connected to one peripheral instance, as shown in the table below. Each peripheral can have one or more interrupt flags, which are located in the peripheral’s Interrupt Flag Status and Clear (INTFLAG) register.
The interrupt flag is set when the interrupt condition occurs. Each interrupt in the peripheral can be individually enabled by writing a one to the corresponding bit in the peripheral’s Interrupt Enable Set (INTENSET) register, and disabled by writing a one to the corresponding bit in the peripheral’s Interrupt Enable Clear (INTENCLR) register.
An interrupt request is generated by the peripheral when the interrupt flag is set and the corresponding interrupt is enabled.
The interrupt requests for one peripheral are ORed together at the system level, generating one interrupt request for each peripheral. An interrupt request will set the corresponding interrupt pending bit in the NVIC interrupt pending registers (SETPEND/CLRPEND bits in ISPR/ICPR).
For the NVIC to activate the interrupt, it must be enabled in the NVIC interrupt enable register (SETENA/CLRENA bits in ISER/ICER). The NVIC interrupt priority registers, IPR0–IPR7, provide a priority field for each interrupt.
| Vector Number | Interrupt Vector | Interrupt Source | Description |
|---|---|---|---|
| NMI | NMI | NMI | Non-Maskable Interrupt from the EIC |
| 0 | SYSTEM | CKRDY | Clock Ready interrupt from MCLK |
| OSCHFRDY | OSCHF is ready interrupt from OSCCTRL | ||
| XOSC32KRDY | XOSC32K ready interrupt from OSCCTRL | ||
| CLKFAIL | XOSC32K has failed interrupt from OSCCTRL | ||
| OSC32KRDY | OSC32K ready interrupt from OSCCTRL | ||
| VDDIO2LPMPOR | VDDIO2 Low-Power Mode POR interrupt from SUPC | ||
| VDDIO2OK | VDDIO2 OK interrupt from SUPC | ||
| VLM | Voltage Level Monitor interrupt from SUPC | ||
| BODVDDRDY | VDD Brown-Out interrupt Detector Ready interrupt from SUPC | ||
| FLASH | Access Error is detected by client Flash | ||
| HSRAMCM0P | Access Error is detected by client SRAMCM0P | ||
| HSRAMDSU | Access Error is detected by client SRAMDSU | ||
| APBB | Access Error is detected by client APBB | ||
| APBA | Access Error is detected by client APBA | ||
| APBC | Access Error is detected by client APBC | ||
| SRAMDMAC | Access Error is detected by client SRAMDMAC | ||
| BROM | Access Error is detected by client BROM | ||
| PAC | Peripheral Access Error occurs while accessing PAC | ||
| PM | Peripheral Access Error occurs while accessing PM | ||
| MCLK | Peripheral Access Error occurs while accessing MCLK | ||
| RSTC | Peripheral Access Error occurs while accessing RSTC | ||
| OSCCTRL | Peripheral Access Error occurs while accessing OSCCTRL | ||
| SUPC | Peripheral Access Error occurs while accessing SUPC | ||
| GCLK | Peripheral Access Error occurs while accessing GCLK | ||
| WDT | Peripheral Access Error occurs while accessing WDT | ||
| RTC | Peripheral Access Error occurs while accessing RTC | ||
| EIC | Peripheral Access Error occurs while accessing EIC | ||
| PORT | Peripheral Access Error occurs while accessing PORT | ||
| DSU | Peripheral Access Error occurs while accessing DSU | ||
| NVMCTRL | Peripheral Access Error occurs while accessing NVMCTRL | ||
| DMAC | Peripheral Access Error occurs while accessing DMAC | ||
| MTB | Peripheral Access Error occurs while accessing MTB | ||
| HMATRIXHS | Peripheral Access Error occurs while accessing HMATRIXHS | ||
| EVSYS | Peripheral Access Error occurs while accessing EVSYS | ||
| SERCOMn | Peripheral Access Error occurs while accessing SERCOMn | ||
| TCn | Peripheral Access Error occurs while accessing TCn | ||
| TCCn | Peripheral Access Error occurs while accessing TCCn | ||
| ADC0 | Peripheral Access Error occurs while accessing ADC0 | ||
| AC | Peripheral Access Error occurs while accessing AC | ||
| CCL | Peripheral Access Error occurs while accessing CCL | ||
| PTC | Peripheral Access Error occurs while accessing PTC | ||
| SYSCTRL | Peripheral Access Error occurs while accessing SYSCTRL | ||
| 1 | WDT | EW | Early Warning interrupt from WDT |
| 2 | RTC | OVF | Overflow interrupt from RTC |
| CMPn/ALARMn | Compare n interrupt (Mode 0 and 1)/Alarm n interrupt (Mode 2) from RTC | ||
| PERn | Periodic Interval n interrupt from RTC | ||
| 3 | EIC | EXTINTn | External Interrupt n from the EIC |
| 4 | NVMCTRL | ERROR | Error interrupt from NVMCTRL |
| READY | Flash ready interrupt from NVMCTRL | ||
| 5 | DMAC | TERR | Transfer error interrupt from DMAC |
| TCMPL | Transfer complete interrupt from DMAC | ||
| SUSP | Suspend interrupt from DMAC | ||
| 6 | EVSYS | OVRn | Overrun Channel n interrupt from EVSYS |
| EVDn | Event Detected Channel n interrupt from EVSYS | ||
| 7 | SERCOM0 | DRE | Data Register Empty from SERCOM0 |
| RXC | Receive Complete from SERCOM0 | ||
| TXC | Transmit Complete from SERCOM0 | ||
| RXS | Receive Start from SERCOM0 | ||
| CTSIC | Clear to Send Input Change from SERCOM0 | ||
| RXBRK | Received Break from SERCOM0 | ||
| SSL | SPI Select Low from SERCOM0 | ||
| DRDY | Data Ready from SERCOM0 | ||
| AMATCH | Address Match from SERCOM0 | ||
| PREC | Stop Received from SERCOM0 | ||
| ERROR | Error from SERCOM0 | ||
| 8 | SERCOM1 | DRE | Data Register Empty from SERCOM1 |
| RXC | Receive Complete from SERCOM1 | ||
| TXC | Transmit Complete from SERCOM1 | ||
| RXS | Receive Start from SERCOM1 | ||
| CTSIC | Clear to Send Input Change from SERCOM1 | ||
| RXBRK | Received Break from SERCOM1 | ||
| SSL | SPI Select Low from SERCOM1 | ||
| DRDY | Data Ready from SERCOM1 | ||
| AMATCH | Address Match from SERCOM1 | ||
| PREC | Stop Received from SERCOM1 | ||
| ERROR | Error from SERCOM1 | ||
| 9 | TC0 | OVF | Overflow interrupt from TC0 |
| ERR | Error interrupt from TC0 | ||
| MCn | Match or Capture Channel n=(0,1) interrupt from TC0 | ||
| 10 | TC1 | OVF | Overflow interrupt from TC1 |
| ERR | Error interrupt from TC1 | ||
| MCn | Match or Capture Channel n=(0,1) interrupt from TC1 | ||
| 11 | TC2 | OVF | Overflow interrupt from TC2 |
| ERR | Error interrupt from TC2 | ||
| MCn | Match or Capture Channel n=(0,1) interrupt from TC2 | ||
| 12 | TCC0 | OVF | Overflow interrupt from TCC0 |
| TRG | Retrigger interrupt from TCC0 | ||
| CNT | Counter interrupt from TCC0 | ||
| ERR | Error interrupt from TCC0 | ||
| UFS | Non-Recoverable Update Fault interrupt from TCC0 | ||
| DFS | Non-Recoverable Debug Fault interrupt from TCC0 | ||
| FAULTx | Recoverable Fault x interrupt from TCC0 | ||
| FAULTn | Non-Recoverable Fault n interrupt from TCC0 | ||
| MCn | Match or Capture Channel n interrupt from TCC0 | ||
| 13 | ADC0 | TRIGOVR | Trigger Overrun interrupt from ADC0 |
| SAMPOVR | Sample Overwrite interrupt from ADC0 | ||
| RESOVR | Result Overwrite interrupt from ADC0 | ||
| RESRDY | Result Ready interrupt from ADC0 | ||
| WCMP | Window Comparator interrupt from ADC0 | ||
| SAMPRDY | Sample Ready interrupt from ADC0 | ||
| 14 | AC | COMPn | Comparator n interrupt from AC |
| WINn | Window n interrupt from AC | ||
| 15-31 | - | - | Reserved |