9.5 Synchronous and Asynchronous Clocks

As the CPU and peripherals can be clocked from different clock domains, peripheral accesses by the CPU need to be synchronized. In these cases, the peripheral includes a Synchronization Busy (SYNCBUSY) register that can be used to check if a synchronization operation is complete.

In the data sheet, references to Synchronous Clocks refer to the CPU and bus clocks (MCLK), while asynchronous clocks are those generated by the Generic Clock Controller (GCLK).