6 Functional Description

The AT25320B/AT25640B is designed to interface directly with the synchronous Serial Peripheral Interface (SPI) of the 6805 and 68HC11 series of microcontrollers.

The AT25320B/AT25640B utilizes an 8-bit instruction register. The list of instructions and their operation codes are contained in Table 6-1. All instructions, addresses and data are transferred with the MSb first and start with a high-to-low CS transition.

Write Enable (WREN):

The device will power-up in the Write Disable state when V_CC is applied. All programming instructions must, therefore, be preceded by a Write Enable instruction.

Write Disable (WRDI):

To protect the device against inadvertent writes, the Write Disable instruction disables all programming modes. The WRDI instruction is independent of the status of the WP pin.

Read STATUS Register (RDSR):

The Read STATUS Register instruction provides access to the STATUS register. The Ready/Busy and Write Enable status of the device can be determined by the RDSR instruction. Similarly, the Block Write Protection bits indicate the extent of protection employed. These bits are set by using the WRSR instruction.

Write STATUS Register (WRSR):

The WRSR instruction allows the user to select one of four levels of protection. The AT25320B/AT25640B is divided into four array segments. One-quarter, one-half or all of the memory segments can be protected. Data within any selected segment will, therefore, be read-only. The Block Write Protection levels and corresponding STATUS register control bits are shown in Table 6-4.

The three bits BP0, BP1 and WPEN are nonvolatile cells that have the same properties and functions as the regular memory cells (e.g., WREN, t_WC, RDSR).

The WRSR instruction also allows the user to enable or disable the Write-Protect (WP) pin through the use of the Write-Protect Enable (WPEN) bit. Hardware Write Protection is enabled when the WP pin is low and the WPEN bit is set to a logic '1'. Hardware Write Protection is disabled when either the WP pin is high or the WPEN bit is set to a logic '0'. When the device is Hardware Write-Protected, writes to the STATUS register, including the Block Protect bits and the WPEN bit, and the block-protected sections in the memory array are disabled. Writes are only allowed to sections of the memory that are not block-protected.

Read Sequence (READ):

Reading the AT25320B/AT25640B via the Serial Output (SO) pin requires the following sequence. After the CS line is pulled low to select a device, the READ instruction is transmitted via the SI line followed by the byte address to be read (A15 – A0, see Table 6-6). Upon completion, any data on the SI line will be ignored. The data (D7 – D0) at the specified address is then shifted out onto the SO line. If only one byte is to be read, the CS line should be driven high after the data comes out. The read sequence can be continued since the byte address is automatically incremented and data will continue to be shifted out. When the highest address is reached, the address counter will roll over to the lowest address allowing the entire memory to be read in one continuous read cycle.

Write Sequence (WRITE):

In order to program the AT25320B/AT25640B, two separate instructions must be executed. First, the device must be write enabled via the WREN instruction. Then, a WRITE instruction may be executed. Also, the address of the memory location(s) to be programmed must be outside the protected address field location selected by the Block Write Protection level. During an internal write cycle, all instructions will be ignored except the RDSR instruction.

A WRITE instruction requires the following sequence. After the CS line is pulled low to select the device, the WRITE instruction is transmitted via the SI line followed by the byte address (A15 – A0) and the data (D7 – D0) to be programmed (see Table 6-6). Programming will start after the CS pin is brought high. The low-to-high transition of the CS pin must occur during the SCK low-time immediately after clocking in the D0 (LSb) data bit.

The Ready/Busy status of the device can be determined by initiating a Read STATUS Register (RDSR) instruction. If Bit 0 = 1, the write cycle is still in progress. If Bit 0 = 0, the write cycle has ended. Only the RDSR instruction is enabled during the write programming cycle.

The AT25320B/AT25640B is capable of a 32-byte page write operation. After each byte of data is received, the five low-order address bits are internally incremented by one; the high-order bits of the address will remain constant. If more than 32 bytes of data are transmitted, the address counter will roll over and the previously written data will be overwritten. The AT25320B/AT25640B is automatically returned to the write disable state at the completion of a write cycle.

Note: If the device is not write enabled, it will ignore the WRITE instruction and will return to the Standby state when CS is brought high. A new CS falling edge is required to reinitiate the serial communication.