2.1 PPS Input Selection Register Details

Table 18-1 PPS Input Selection Register Details has been updated as follows:

Table 2-1. PPS Input Selection Register Details
PeripheralPPS Input RegisterDefault Pin Selection
 at PORRegister Reset Value
 at PORPORT From Which Input Is Available
Interrupt 0INT0PPSRB00x08AB——————
Interrupt 1INT1PPSRB10x09—BC—————
Interrupt 2INT2PPSRB20x0A—B—D————
Interrupt 3INT3PPSRB30x0B—B——E———
Timer0 ClockT0CKIPPSRA40x04AB——————
Timer1 ClockT1CKIPPSRC00x10——CD————
Timer1 GateT1GPPSRB50x0D—BC—————
Timer3 ClockT3CKIPPSRB50x0D—BC—————
Timer3 GateT3GPPSRA50x05A—C—————
Timer5 ClockT5CKIPPSRD10x19———DE———
Timer5 GateT5GPPSRG40x34————E—G—
Timer7 ClockT7CKIPPSRG40x34————E—G—
Timer7 GateT7GPPSRD10x19———DE———
Timer2 ClockT2INPPSRA10x01A—C—————
Timer4 ClockT4INPPSRE40x24—B——E———
Timer6 ClockT6INPPSRC10x11—BC—————
Timer8 ClockT8INPPSRA00x00A———E———
ADC Conversion TriggerADACTPPSRH10x39——C————H
CCP1CCP1PPSRE50x25——C—E———
CCP2CCP2PPSRE40x24——C—E———
CCP3CCP3PPSRE60x26——C—E———
CCP4CCP4PPSRG30x33————E—G—
CCP5CCP5PPSRG40x34————E—G—
SMT1 WindowSMT1WINPPSRE60x26——C—E———
SMT1 SignalSMT1SIGPPSRE70x27——C—E———
SMT2 WindowSMT2WINPPSRG60x36——C———G—
SMT2 SignalSMT2SIGPPSRG70x37——C———G—
CWGCWG1PPSRC20x12——C—————
DSM Carrier LowMDCARLPPSRD30x1B———D———H
DSM Carrier HighMDCARHPPSRD40x1C———D———H
DSM SourceMDSRCPPSRD50x1D———D———H
MSSP1 ClockSSP1CLKPPSRC30x13—BC—————
MSSP1 DataSSP1DATPPSRC40x14—BC—————
MSSP1 Client SelectSSP1SSPPSRF70x2F—B————F—
MSSP2 ClockSSP2CLKPPSRD60x1E—B—D————
MSSP2 DataSSP2DATPPSRD50x1D—B—D————
MSSP2 Client SelectSSP2SSPPSRD70x1F—B—D————
EUSART1 ReceiveRX1PPSRC70x17——CD————
EUSART1 ClockCK1PPSRC60x16——CD————
EUSART2 ReceiveRX2PPSRG20x32———D——G—
EUSART2 ClockCK2PPSRG10x31———D——G—
EUSART3 ReceiveRX3PPSRE10x21—B——E———
EUSART3 ClockCK3PPSRE00x20—B——E———
EUSART4 ReceiveRX4PPSRC10x11—BC—————
EUSART4 ClockCK4PPSRC00x10—BC—————
EUSART5 ReceiveRX5PPSRE30x23————E—G—
EUSART5 ClockCK5PPSRE20x22————E—G—