Introduction

Wafer-Level Chip-Scale Packages (WLCSP) are the smallest possible packages that scale down to the same size as the silicon die. These are manufactured such that bumping, ball drop, and testing are done at the wafer-level. It is after these processes that the wafer is diced and made available, usually in tape and reel media. For conventional lead frame-based packages, such as QFPs and QFNs, the wafer is diced first, and then the die is attached on the lead frame with the wire bonds followed by encapsulation in a mold compound resulting in packaged silicon. Testing is done on the packaged silicon and is made available in tray, tube, or tape and reel media.

The inherent manufacturing process of WLCSP eliminates the lead frame and mold compound, making it a fragile package compared to the lead-frame based packages. Due to this, WLCSP packages are deemed undesirable for typical automotive and industrial applications, while their small size earns a distinction in space-constrained applications, such as smart phones, wearables, headphones, and tablet accessories like stylus pens. The smallest WLCSP package within the Microchip 32-bit portfolio is a SAMD11 Cortex® M0+ MCU with 20 leads and a 1.9 mm x 2.4 mm size. WLCSPs are also offered for higher performance Cortex M4F families including the SAM D5x/E5x and SAMG5x series. In addition to WLCSP packages, Microchip offers tiny lead-frame based packages for their 32-bit PIC® and SAM MCU portfolios, which are robust and easier to assemble on the PCB. These include a 24-pin VQFN 4 mm x 4 mm, and 32-pin VQFN 5 mm x 5 mm packages. Depending on the type of space-constrained applications, these VQFNs are more popular and can be considered an alternative to WLCSPs where higher temperatures, mechanical stress, handling, and assembling are of concern. To help customers with the assembly and surface mounting of the WLCSP packages, guidelines are provided in the later sections of this document.