7.1 How Does It Work?

What's in the silicon that allows it to communicate with the MPLAB ICE 4 In-Circuit Emulator?

MPLAB ICE 4 can communicate with Flash silicon via the ICSP and other target interfaces. It uses the debug executive located in dedicated memory. For legacy 8-bit PIC devices, the debug executive resides in Program memory.

How is the throughput of the processor affected by having to run the debug executive?

The debug executive doesn't run while in Run mode, so there is no throughput reduction when running your code, i.e., the debugger doesn’t ‘steal’ any cycles from the target device.

How does MPLAB X IDE interface with the MPLAB ICE 4 In-Circuit Emulator to allow more features than older debug tools?

MPLAB ICE 4 communicates using the debug executive located in a dedicated area of memory. The debug executive is streamlined for more efficient communication. The debugger contains an FPGA, large SRAM Buffers (1Mx8), and a High-Speed USB interface. Program memory image is downloaded and is contained in the SRAM to allow faster programming. The FPGA in the debugger serves as an accelerator for interfacing with the device in-circuit debugger modules.

On traditional debuggers, the data must come out on the bus in order to perform a complex trigger on that data. Is this also required on the MPLAB ICE 4 In-Circuit Emulator? For example, could I halt, based on a flag going high?

Traditional debuggers use a special debugger chip (-ME) for monitoring. There is no -ME with theMPLAB ICE 4, so there are no buses to monitor externally. With the MPLAB ICE 4, rather than using external breakpoints, the built-in breakpoint circuitry of the debug engine is used – the buses and breakpoint logic are monitored inside the part.

Does the MPLAB ICE 4 In-Circuit Emulator have complex breakpoints?

Yes. You can break based on a value in a data memory location. You can also do sequenced breakpoints, where several events have to occur before it breaks. However, you can only do two sequences. You can also do the AND condition and do PASS counts.

What limitations are there with the standard cable?

The standard ICSP-RJ11 cable maximum clock frequency is approximately 15 MHz. Device interrogation during debugging occurs at frequencies below this rate regardless of the CPU clock rate. However, some advanced functions are synchronous to the CPU bus cycle (like instrumented trace and data capture). During data capture and when the CPU runs at its highest speed (40 MIPS for example), the actual clock rate through the cable would exceed 15 MHz. In these instances, trace and data capture cannot run reliably and the ICSP-RJ11 cable cannot be used.

Will this slow down the running of the program?

There is no cycle stealing with the MPLAB ICE 4. The output of data is performed by the state machine in the silicon.

Is it possible to debug a dsPIC DSC device running at any speed?

The MPLAB ICE 4 is capable of debugging at any device speed as specified in the device’s data sheet.