6 Appendix B: Pinout Descriptions and Configuration Words

Table 6-1. Programming Pin Locations By Package Type
Device Package Package Code VDD VSS MCLR ICSPCLK ICSPDAT
PIN PIN PIN PORT PIN PORT PIN PORT

PIC16F13113

PIC16F13114

PIC16F13115

8-Pin PDIP P 1 8 4 RA3 6 RA1 7 RA0
8-Pin SOIC SN 1 8 4 RA3 6 RA1 7 RA0
8-Pin DFN MF 1 8 4 RA3 6 RA1 7 RA0

PIC16F13123

PIC16F13124

PIC16F13125

14-Pin PDIP P 1 14 4 RA3 12 RA1 13 RA0
14-Pin SOIC SL 1 14 4 RA3 12 RA1 13 RA0
14-Pin TSSOP ST 1 14 4 RA3 12 RA1 13 RA0
16-Pin VQFN MG 16 13 3 RA3 11 RA1 12 RA0

PIC16F13143

PIC16F13144

PIC16F13145

20-Pin PDIP P 1 20 4 RA3 18 RA1 19 RA0
20-Pin SOIC SO 1 20 4 RA3 18 RA1 19 RA0
20-Pin SSOP SS 1 20 4 RA3 18 RA1 19 RA0
20-Pin VQFN REB 18 17 1 RA3 15 RA1 16 RA0
Note: The most current drawings are located in the Microchip Packaging Specification, DS00000049 (http://www.microchip.com/packaging).