2 Memory Map

This section provides details on how the memory is organized for this device.

Table 2-1. Program Memory Map
AddressDevice
PIC16F131x3PIC16F131x4PIC16F131x5
0000h to 07FFhProgram Flash Memory (2 KW)(1)Program Flash Memory (4 KW)(1)Program Flash Memory (8 KW)(1)
0800h to 0FFFhNot Present(2)
1000h to 1FFFhNot Present(2)
4000h to 7FFFhNot Present(2)
8000h to 8003hUser IDs (4 Words)(3)
8004hReserved
8005hRevision ID (1 Word)(3)(4)(5)
8006hDevice ID (1 Word)(3)(4)(5)
8007h to 800BhConfiguration Words(3)
800Ch to 80FFhReserved
8100h to 813FhDevice Information Area (DIA)(3)(5)
8140h to 81FFhReserved
8200h to 82FFhDevice Configuration Information(3)(4)(5)
8300h to FFFFhReserved
Note:
  1. Storage Area Flash (SAF) is implemented as the last 128 words of Program Flash Memory, if enabled.
  2. The addresses do not roll over. The region is read as ‘0’. When accessing these areas using the NVMCON registers, reads and/or writes will set the NVMERR bit.
  3. Not code-protected.
  4. Hard-coded in silicon.
  5. This region cannot be written by the user, and is not affected by a Bulk Erase.