21.1 Features

  • True 16-bit Design (i.e., allows 16-bit PWM)
  • Two independent Output Compare Units
  • Double Buffered Output Compare Registers
  • One Input Capture Unit
  • Input Capture Noise Canceler
  • Clear Timer on Compare Match (Auto Reload)
  • Glitch-free, Phase Correct Pulse Width Modulator (PWM)
  • Variable PWM Period
  • Frequency Generator
  • External Event Counter
  • Independent interrupt Sources (TOV, OCFA, OCFB, and ICF)