31.3.1 Store Program Memory Control and Status Register
The Store Program Memory Control and Status Register contains the control bits needed to control the Program memory operations.
When addressing I/O Registers as data space using LD and ST instructions, the provided offset must be used. When using the I/O specific commands IN and OUT, the offset is reduced by 0x20, resulting in an I/O address offset within 0x00 - 0x3F.
Name: | SPMCSR |
Offset: | 0x57 |
Reset: | 0x00 |
Property: | When addressing I/O Registers as data space the offset address is 0x37 |
Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
SPMIE | RWWSB | SIGRD | RWWSRE | BLBSET | PGWRT | PGERS | SPMEN | ||
Access | R/W | R | R | R/W | R/W | R/W | R/W | R/W | |
Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bit 7 – SPMIE SPM Interrupt Enable
Bit 6 – RWWSB Read-While-Write Section Busy
Bit 5 – SIGRD Signature Row Read
Bit 4 – RWWSRE Read-While-Write Section Read Enable
Bit 3 – BLBSET Boot Lock Bit Set
Bit 2 – PGWRT Page Write
Bit 1 – PGERS Page Erase
Bit 0 – SPMEN Store Program Memory
This bit enables the SPM instruction for the next four clock cycles. If written to one together with either RWWSRE, BLBSET, PGWRT, or PGERS, the following SPM instruction will have a special meaning, see description above. If only SPMEN is written, the following SPM instruction will store the value in R1:R0 in the temporary page buffer addressed by the Z-pointer. The LSB of the Z-pointer is ignored. The SPMEN bit will auto-clear upon completion of an SPM instruction, or if no SPM instruction is executed within four clock cycles. During Page Erase and Page Write, the SPMEN bit remains high until the operation is completed.
Writing any other combination than “0x10001”, “0x01001”, “0x00101”, “0x00011” or “0x00001” in the lower five bits will have no effect.