23.8 Timer/Counter Timing Diagrams
The following figures show the Timer/Counter in synchronous mode, and the timer clock (clkT2) is therefore shown as a clock enable signal. In asynchronous mode, clkI/O should be replaced by the Timer/Counter Oscillator clock. The figures include information on when Interrupt Flags are set. The following figure contains timing data for basic Timer/Counter operation. The figure shows the count sequence close to the MAX value in all modes other than phase correct PWM mode.
The following figure shows the same timing data, but with the prescaler enabled.
The following figure shows the setting of OCF2A in all modes except CTC mode.
The following figure shows the setting of OCF2A and the clearing of TCNT2 in CTC mode.