33.1 Program And Data Memory Lock Bits

The ATmega48PB provides two Lock bits and the other devices provides Lock bits. These can be left unprogrammed ('1') or can be programmed ('0') to obtain the additional features listed in Table. Lock Bit Protection Modes in this section. The Lock bits can only be erased to “1” with the Chip Erase command.

The ATmega48PB has no separate Boot Loader section, and the Store Program Memory (SPM) instruction is enabled for the whole Flash if the SELFPRGEN fuse is programmed (“0”). Otherwise the SPM instruction is disabled.

Table 33-1. Lock Bit Byte(1)
Lock Bit ByteBit No.DescriptionDefault Value
7–1 (unprogrammed)
6–1 (unprogrammed)
BLB12(2)5Boot Lock bit1 (unprogrammed)
BLB11(2)4Boot Lock bit1 (unprogrammed)
BLB02(2)3Boot Lock bit1 (unprogrammed)
BLB01(2)2Boot Lock bit1 (unprogrammed)
LB21Lock bit1 (unprogrammed)
LB10Lock bit1 (unprogrammed)
Note:
  1. '1' means unprogrammed, '0' means programmed.
  2. Only on ATmega88PB and ATmega168PB.
Table 33-2. Lock Bit Protection Modes(1)(2)
Memory Lock BitsProtection Type
LB ModeLB2LB1
111No memory lock features enabled.
210Further programming of the Flash and EEPROM is disabled in Parallel and Serial Programming mode. The Fuse bits are locked in both Serial and Parallel Programming mode.(1)
300Further programming and verification of the Flash and EEPROM is disabled in Parallel and Serial Programming mode. The Boot Lock bits and Fuse bits are locked in both Serial and Parallel Programming mode.(1)
Note:
  1. Program the Fuse bits and Boot Lock bits before programming the LB1 and LB2.
  2. '1' means unprogrammed, '0' means programmed.
Table 33-3. Lock Bit Protection - BLB0 Mode(1)(2). (Only ATmega88PB and ATmega168PB.)
BLB0 ModeBLB02BLB01
111No restrictions for SPM or Load Program Memory (LPM) instruction accessing the Application section.
210SPM is not allowed to write to the Application section.
300SPM is not allowed to write to the Application section, and LPM executing from the Boot Loader section is not allowed to read from the Application section. If Interrupt Vectors are placed in the Boot Loader section, interrupts are disabled while executing from the Application section.
401LPM executing from the Boot Loader section is not allowed to read from the Application section. If Interrupt Vectors are placed in the Boot Loader section, interrupts are disabled while executing from the Application section.
Table 33-4. Lock Bit Protection - BLB1 Mode(1)(2) (Only ATmega88PB and ATmega168PB.)
BLB1 ModeBLB12BLB11
111No restrictions for SPM or LPM accessing the Boot Loader section.
210SPM is not allowed to write to the Boot Loader section.
300SPM is not allowed to write to the Boot Loader section, and LPM executing from the Application section is not allowed to read from the Boot Loader section. If Interrupt Vectors are placed in the Application section, interrupts are disabled while executing from the Boot Loader section.
401LPM executing from the Application section is not allowed to read from the Boot Loader section. If Interrupt Vectors are placed in the Application section, interrupts are disabled while executing from the Boot Loader section.
Note:
  1. Program the Fuse bits and Boot Lock bits before programming the LB1 and LB2.
  2. '1' means unprogrammed; '0' means programmed.