15.11.2 MCU Control Register
When addressing I/O Registers as data space using LD and ST instructions, the provided offset must be used. When using the I/O specific commands IN and OUT, the offset is reduced by 0x20, resulting in an I/O address offset within 0x00 - 0x3F.
Name: | MCUCR |
Offset: | 0x55 |
Reset: | 0x00 |
Property: | When addressing as I/O Register: address offset is 0x35 |
The MCU Control Register controls the placement of the Interrupt Vector table in order to move interrupts between application and boot space. (For ATmega88PB and ATmega168PB )
Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
BODS | BODSE | PUD | IVSEL | IVCE | |||||
Access | R/W | R/W | R/W | R/W | R/W | ||||
Reset | 0 | 0 | 0 | 0 | 0 |
Bit 6 – BODS BOD Sleep
The BODS bit must be written to '1' in order to turn off BOD during sleep. Writing to the BODS bit is controlled by a timed sequence and the enable bit BODSE. To disable BOD in relevant sleep modes, both BODS and BODSE must first be written to '1'. Then, BODS must be written to '1' and BODSE must be written to zero within four clock cycles.
The BODS bit is active three clock cycles after it is set. A sleep instruction must be executed while BODS is active in order to turn off the BOD for the actual sleep mode. The BODS bit is automatically cleared after three clock cycles.
Bit 5 – BODSE BOD Sleep Enable
BODSE enables setting of BODS control bit, as explained in BODS bit description. BOD disable is controlled by a timed sequence.
Bit 4 – PUD Pull-up Disable
When this bit is written to one, the pull-ups in the I/O ports are disabled even if the DDxn and PORTxn Registers are configured to enable the pull-ups ({DDxn, PORTxn} = 0b01).
Bit 1 – IVSEL Interrupt Vector Select
When the IVSEL bit is cleared (zero), the Interrupt Vectors are placed at the start of the Flash memory. When this bit is set (one), the Interrupt Vectors are moved to the beginning of the Boot Loader section of the Flash. The actual address of the start of the Boot Flash Section is determined by the BOOTSZ Fuses. To avoid unintentional changes of Interrupt Vector tables, a special write procedure must be followed to change the IVSEL bit:
- Write the Interrupt Vector Change Enable (IVCE) bit to one.
- Within four cycles, write the desired value to IVSEL while writing a zero to IVCE.
Interrupts will automatically be disabled while this sequence is executed. Interrupts are disabled in the cycle IVCE is set, and they remain disabled until after the instruction following the write to IVSEL. If IVSEL is not written, interrupts remain disabled for four cycles. The I-bit in the Status Register is unaffected by the automatic disabling.
Bit 0 – IVCE Interrupt Vector Change Enable
Assembly Code Example |
Move_interrupts: ; Get MCUCR in r16, MCUCR mov r17, r16 ; Enable change of Interrupt Vectors ori r16, (1<<IVCE) out MCUCR, r16 ; Move interrupts to Boot Flash section ori r17, (1<<IVSEL) out MCUCR, r17 ret |
C Code Example |
void Move_interrupts(void) { uchar temp; /* GET MCUCR*/ temp = MCUCR; /* Enable change of Interrupt Vectors */ MCUCR = temp|(1<<IVCE); /* Move interrupts to Boot Flash section */ MCUCR = temp|(1<<IVSEL); } |