2 Pin Descriptions
The descriptions of the pins are listed in Table 2-1.
| Name | 8-Lead PDIP | 8-Lead SOIC | 8-Lead TSSOP | 5-Lead SOT23 | 8-Pad UDFN(1) | 8-Ball VFBGA | Function |
|---|---|---|---|---|---|---|---|
| NC | 1 | 1 | 1 | － | 1 | 1 | No Connect |
| NC | 2 | 2 | 2 | － | 2 | 2 | No Connect |
| A2(2) | 3 | 3 | 3 | － | 3 | 3 | Device Address Input |
| GND | 4 | 4 | 4 | 2 | 4 | 4 | Ground |
| SDA | 5 | 5 | 5 | 3 | 5 | 5 | Serial Data |
| SCL | 6 | 6 | 6 | 1 | 6 | 6 | Serial Clock |
| WP(2) | 7 | 7 | 7 | 5 | 7 | 7 | Write-Protect |
| VCC | 8 | 8 | 8 | 4 | 8 | 8 | Device Power Supply |
Note:
- The exposed pad on the this package can be connected to GND or left floating.
- If the A2 or WP pins are not driven, they are internally pulled down to GND. In order to operate in a wide variety of application environments, the pull-down mechanism is intentionally designed to be somewhat strong. Once these pins are biased above the CMOS input buffer’s trip point (~0.5 x VCC), the pull‑down mechanism disengages. Microchip recommends connecting these pins to a known state whenever possible.