33.3.1.1 UPDI UART
The communication is initiated from the debugger/programmer side. Every transmission must start with a SYNCH character, which the UPDI can use to recover the transmission baud rate and store this setting for the incoming data. The baud rate set by the SYNCH character will be used for both reception and transmission of the subsequent instruction and data bytes. See the UPDI Instruction Set section for details on when the next SYNCH character is expected in the instruction stream.
There is no writable Baud Rate register in the UPDI, so the baud rate sampled from the SYNCH character is used for data recovery when sampling the data byte.
The transmission baud rate of the PHY layer is related to the selected UPDI clock, which
can be adjusted by writing to the UPDI Clock Divider Select (UPDICLKSEL) bit field in
the ASI Control A (UPDI.ASI_CTRLA) register. The receive and transmit baud rates are
always the same within the accuracy of the auto-baud.
| UPDICLKSEL[1:0] | Max. Recommended Baud Rate | Min. Recommended Baud Rate |
|---|---|---|
0x1 (16 MHz) | 0.9 Mbps | 0.300 kbps |
0x2 (8 MHz) | 450 kbps | 0.150 kbps |
0x3 (4 MHz) - Default | 225 kbps | 0.075 kbps |
The UPDI Baud Rate Generator utilizes fractional baud counting to minimize the
transmission error. With the fixed frame format used by the UPDI, the maximum and
recommended receiver transmission error limits can be seen in Table 33-2.
| Data + Parity Bits | Rslow | Rfast | Max. Total Error [%] | Recommended Max. RX Error [%] |
|---|---|---|---|---|
| 9 | 96.39 | 104.76 | +4.76/-3.61 | +1.5/-1.5 |