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tinyAVR® 1-series ATtiny417/814/816/817
Introduction
Features
1 Silicon Errata and Data Sheet Clarification Document
2 tinyAVR® 1-series Overview
2.1 Configuration Summary
3 Block Diagram
4 Pinout
4.1 14-Pin SOIC
4.2 20-Pin SOIC
4.3 20-Pin VQFN
4.4 24-Pin VQFN
5 I/O Multiplexing and Considerations
5.1 Multiplexed Signals
6 Memories
6.1 Overview
6.2 Memory Map
6.3 In-System Reprogrammable Flash Program Memory
6.4 SRAM Data Memory
6.5 EEPROM Data Memory
6.6 User Row
6.7 Signature Bytes
6.8 I/O Memory
6.9 Memory Section Access from CPU and UPDI on Locked Device
6.10 Configuration and User Fuses (FUSE)
7 Peripherals and Architecture
7.1 Peripheral Address Map
7.2 Interrupt Vector Mapping
7.3 System Configuration (SYSCFG)
8 AVR® CPU
8.1 Features
8.2 Overview
8.3 Architecture
8.4 Arithmetic Logic Unit (ALU)
8.5 Functional Description
8.6 Register Summary
8.7 Register Description
9 NVMCTRL - Nonvolatile Memory Controller
9.1 Features
9.2 Overview
9.3 Functional Description
9.4 Register Summary
9.5 Register Description
10 CLKCTRL - Clock Controller
10.1 Features
10.2 Overview
10.3 Functional Description
10.4 Register Summary
10.5 Register Description
11 SLPCTRL - Sleep Controller
11.1 Features
11.2 Overview
11.3 Functional Description
11.4 Register Summary
11.5 Register Description
12 RSTCTRL - Reset Controller
12.1 Features
12.2 Overview
12.3 Functional Description
12.4 Register Summary
12.5 Register Description
13 CPUINT - CPU Interrupt Controller
13.1 Features
13.2 Overview
13.3 Functional Description
13.4 Register Summary
13.5 Register Description
14 EVSYS - Event System
14.1 Features
14.2 Overview
14.3 Functional Description
14.4 Register Summary
14.5 Register Description
15 PORTMUX - Port Multiplexer
15.1 Overview
15.2 Register Summary
15.3 Register Description
16 PORT - I/O Pin Configuration
16.1 Features
16.2 Overview
16.3 Functional Description
16.4 Register Summary - PORTx
16.5 Register Description - PORTx
16.6 Register Summary - VPORTx
16.7 Register Description - VPORTx
17 BOD - Brown-out Detector
17.1 Features
17.2 Overview
17.3 Functional Description
17.4 Register Summary
17.5 Register Description
18 VREF - Voltage Reference
18.1 Features
18.2 Overview
18.3 Functional Description
18.4 Register Summary
18.5 Register Description
19 WDT - Watchdog Timer
19.1 Features
19.2 Overview
19.3 Functional Description
19.4 Register Summary - WDT
19.5 Register Description
20 TCA - 16-bit Timer/Counter Type A
20.1 Features
20.2 Overview
20.3 Functional Description
20.4 Register Summary - Normal Mode
20.5 Register Description - Normal Mode
20.6 Register Summary - Split Mode
20.7 Register Description - Split Mode
21 TCB - 16-Bit Timer/Counter Type B
21.1 Features
21.2 Overview
21.3 Functional Description
21.4 Register Summary
21.5 Register Description
22 TCD - 12-Bit Timer/Counter Type D
22.1 Features
22.2 Overview
22.3 Functional Description
22.4 Register Summary
22.5 Register Description
23 RTC - Real-Time Counter
23.1 Features
23.2 Overview
23.3 Clocks
23.4 RTC Functional Description
23.5 PIT Functional Description
23.6 Events
23.7 Interrupts
23.8 Sleep Mode Operation
23.9 Synchronization
23.10 Debug Operation
23.11 Register Summary
23.12 Register Description
24 USART - Universal Synchronous and Asynchronous Receiver and Transmitter
24.1 Features
24.2 Overview
24.3 Functional Description
24.4 Register Summary
24.5 Register Description
25 SPI - Serial Peripheral Interface
25.1 Features
25.2 Overview
25.3 Functional Description
25.4 Register Summary
25.5 Register Description
26 TWI - Two-Wire Interface
26.1 Features
26.2 Overview
26.3 Functional Description
26.4 Register Summary
26.5 Register Description
27 CRCSCAN - Cyclic Redundancy Check Memory Scan
27.1 Features
27.2 Overview
27.3 Functional Description
27.4 Register Summary - CRCSCAN
27.5 Register Description
28 CCL - Configurable Custom Logic
28.1 Features
28.2 Overview
28.3 Functional Description
28.4 Register Summary
28.5 Register Description
29 AC - Analog Comparator
29.1 Features
29.2 Overview
29.3 Functional Description
29.4 Register Summary
29.5 Register Description
30 ADC - Analog-to-Digital Converter
30.1 Features
30.2 Overview
30.3 Functional Description
30.4 Register Summary - ADCn
30.5 Register Description
31 DAC - Digital-to-Analog Converter
31.1 Features
31.2 Overview
31.3 Functional Description
31.4 Register Summary
31.5 Register Description
32 PTC - Peripheral Touch Controller
32.1 Overview
32.2 Features
32.3 Block Diagram
32.4 Signal Description
32.5 System Dependencies
32.6 Functional Description
33 UPDI - Unified Program and Debug Interface
33.1 Features
33.2 Overview
33.3 Functional Description
33.4 Register Summary
33.5 Register Description
34 Instruction Set Summary
35 Conventions
35.1 Numerical Notation
35.2 Memory Size and Type
35.3 Frequency and Time
35.4 Registers and Bits
35.5 ADC Parameter Definitions
36 Electrical Characteristics
36.1 Disclaimer
36.2 Absolute Maximum Ratings
36.3 General Operating Ratings
36.4 Power Consumption
36.5 Wake-Up Time
36.6 Peripherals Power Consumption
36.7 BOD and POR Characteristics
36.8 External Reset Characteristics
36.9 Oscillators and Clocks
36.10 I/O Pin Characteristics
36.11 TCD
36.12 USART
36.13 SPI
36.14 TWI
36.15 VREF
36.16 ADC
36.17 TEMPSENSE
36.18 DAC
36.19 AC
36.20 PTC
36.21 UPDI Timing
36.22 Programming Time
37 Typical Characteristics
37.1 Power Consumption
37.2 GPIO
37.3 VREF Characteristics
37.4 BOD Characteristics
37.5 ADC Characteristics
37.6 TEMPSENSE Characteristics
37.7 AC Characteristics
37.8 OSC20M Characteristics
37.9 OSCULP32K Characteristics
37.10 TWI SDA Hold Timing
38 Ordering Information
38.1 Product Information
38.2 Product Identification System
39 Package Drawings
39.1 Online Package Drawings
39.2 14-Pin SOIC
39.3 20-Pin SOIC
39.4 20-Pin VQFN
39.5 24-Pin VQFN
39.6 Thermal Considerations
40 Errata
40.1 Errata - ATtiny417/814/816/817
41 Data Sheet Revision History
41.1 Rev. A - 12/2020
41.2 Appendix - Obsolete Revision History
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