30.3.2.4 Changing Channel or Reference Selection
The MUXPOS bit field in the ADCn.MUXPOS register and the REFSEL bit field in the ADCn.CTRLC register are buffered through a temporary register to which the CPU has random access. This ensures that the channel and reference selections only take place at a safe point during the conversion. The channel and reference selections are continuously updated until a conversion is started.
Once the conversion starts, the channel and reference selections are locked to ensure
sufficient sampling time for the ADC. Continuous updating resumes in the last CLK_ADC clock
cycle before the conversion completes (RESRDY bit in the ADCn.INTFLAGS register is set).
The conversion starts on the following rising CLK_ADC clock edge after the STCONV bit is
written to ‘1
’.