28.5.4 LUT n Control B

Note:
  1. SPI connections to the CCL work in Host SPI mode only.
  2. USART connections to the CCL work only when the USART is in one of the following modes:
    • Asynchronous USART
    • Synchronous USART Host
Name: LUTnCTRLB
Offset: 0x06 + n*0x04 [n=0..1]
Reset: 0x00
Property: Enable-Protected

Bit 76543210 
 INSEL1[3:0]INSEL0[3:0] 
Access R/WR/WR/WR/WR/WR/WR/WR/W 
Reset 00000000 

Bits 7:4 – INSEL1[3:0] LUT n Input 1 Source Selection

This bit field selects the source for input 1 of LUT n.

ValueNameDescription
0x0MASKMasked input
0x1FEEDBACKFeedback input
0x2LINKLinked other LUT as input source
0x3EVENT0Event input source 0
0x4EVENT1Event input source 1
0x5IOI/O-pin LUTn-IN1 input source
0x6AC0AC0 OUT input source
0x7TCB0TCB0 WO input source
0x8TCA0TCA0 WO1 input source
0x9TCD0TCD0 WOB input source
0xAUSART0USART0 TXD input source
0xBSPI0SPI0 MOSI input source
Other-Reserved

Bits 3:0 – INSEL0[3:0] LUT n Input 0 Source Selection

This bit field selects the source for input 0 of LUT n.

ValueNameDescription
0x0MASKMasked input
0x1FEEDBACKFeedback input
0x2LINKLinked other LUT as input source
0x3EVENT0Event input source 0
0x4EVENT1Event input source 1
0x5IOI/O-pin LUTn-IN0 input source
0x6AC0AC0 OUT input source
0x7TCB0TCB0 WO input source
0x8TCA0TCA0 WO0 input source
0x9TCD0TCD0 WOA input source
0xAUSART0USART0 XCK input source
0xBSPI0SPI0 SCK input source
Other-Reserved