33.5.7 ASI Control A
Name: | ASI_CTRLA |
Offset: | 0x09 |
Reset: | 0x03 |
Property: | - |
Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
UPDICLKSEL[1:0] | |||||||||
Access | R/W | R/W | |||||||
Reset | 1 | 1 |
Bits 1:0 – UPDICLKSEL[1:0] UPDI Clock Divider Select
Writing these bits selects the UPDI clock output frequency. The default setting after Reset and enable is 4 MHz. Any other clock output selection is only recommended when the BOD is at the highest level. For all other BOD settings, the default 4 MHz selection is recommended.
Value | Description |
---|---|
0x0 | Reserved |
0x1 | 16 MHz UPDI clock |
0x2 | 8 MHz UPDI clock |
0x3 | 4 MHz UPDI clock (Default Setting) |