8.3 Architecture

To maximize performance and parallelism, the AVR CPU uses a Harvard architecture with separate buses for program and data. The instructions in the program memory are executed with a single-level pipeline. While one instruction is being executed, the next instruction is prefetched from the program memory. This enables instructions to be executed on every clock cycle.

Refer to the Instruction Set Summary section for a summary of all AVR instructions.

Figure 8-1. AVR® CPU Architecture