8 Appendix

A value of 00H indicates a JEDEC-specified header. For vendor-specified headers, this field is set to the vendor’s manufacturer ID.

Minor revisions include clarifications or additions in existing reserved locations and do not change the overall SFDP structure. Minor revisions start at 00H.

Major revisions reorganize or add parameters in non-reserved locations and may require BIOS, firmware or hardware changes to access previously defined parameters. Major revisions start at 01H.

Specifies the number of DWORDs in the parameter table.

A 24-bit address that specifies the starting location of this header’s parameter table within the SFDP structure. The address must be DWORD-aligned.

Minor revisions include clarifications or additions in existing reserved locations and do not change the overall SFDP structure. Minor revisions start at 00H.

Major revisions reorganize or add parameters in non-reserved locations and may require BIOS, firmware or hardware changes. Major revisions start at 01H.

Specifies the number of DWORDs in the parameter table.

A 24-bit address that specifies the starting location of this header’s parameter table within the SFDP structure. The address must be DWORD-aligned.

Manufacturer ID (vendor-specified header)

A 24-bit address that specifies the starting location of this header’s parameter table within the SFDP structure. The address must be DWORD-aligned.

00: Reserved

01: 4-Kbyte Erase

10: Reserved

11: Use only when 4-Kbyte erase is unavailable

0: Single-byte programmable devices or buffer-programmable devices with a buffer smaller than 64 bytes (32 words)

1: Buffer-programmable devices with a buffer size of 64 bytes (32 words) or larger

0: Nonvolatile status bits; Write/Erase commands do not require the status register to be written at every power-on

1: Volatile status bits

0: 0x50 enables a status register write when bit A3 is set to 1

1: 0x06 enables a status register write when bit A3 is set to 1

0: (1-1-2) Fast Read not supported

1: (1-1-2) Fast Read supported

Specifies the number of address bytes used for Flash array read, write and erase operations.

00: 3-byte addressing only

01: 3- or 4-byte addressing (defaults to 3-byte mode and enters 4-byte mode on command)

10: 4-byte addressing only

11: Reserved

Indicates that the device supports some form of double transfer rate clocking.

0: DTR not supported

1: DTR clocking supported

Device supports Fast Read operations using a single-input opcode, dual-input address, and dual output.

0: (1-2-2) Fast Read not supported

1: (1-2-2) Fast Read supported

Device supports Fast Read operations using a single-input opcode, quad-input address, and quad-output data.

0: (1-4-4) Fast Read NOT supported

1: (1-4-4) Fast Read supported

Device supports Fast Read operations using a single-input opcode and address, and quad-output data.

0: (1-1-4) Fast Read not supported

1: (1-1-4) Fast Read supported

MC25VF128 = 07FFFFFFH

00100b: 4 dummy clocks (16 dummy bits) are required when using a quad-input address phase instruction

010b: 2 dummy clocks (8 mode bits) are required for a single-input opcode, quad-input address, and quad-output data Fast Read instruction

Opcode for Fast Read operations using a single-input opcode, a quad-input address, and quad-output data

01000b: 8 dummy bits are required when using a Fast Read instruction with a single-input opcode and address, and quad-output data

000b: No mode bits are required when using a Fast Read instruction with a single-input opcode and address, and quad-output data

Opcode for Fast Read operations using a single-input opcode and address, and quad-output data

01000b: 8 dummy clocks are required when using a Fast Read instruction with a single-input opcode and address, and dual-output data

000b: No mode bits are required when using a Fast Read instruction with a single-input opcode and address, and quad-output data

Opcode for Fast Read operations using a single-input opcode and address, and dual-output data

00000b: 0 dummy clock cycles are required

00010b: 2 dummy clock cycles are required

010b: 2 clock cycles of mode bits are required

Opcode for Fast Read operations using a single-input opcode, dual-input address, and dual-output data

Device supports Fast Read using dual-input opcode and address, and dual-output data

0: (2-2-2) Fast Read not supported

1: (2-2-2) Fast Read supported

Device supports Fast Read operations using a quad-input opcode and address, and quad-output data

0: (4-4-4) Fast Read not supported

1: (4-4-4) Fast Read supported

00000b: No dummy bits are required

000b: No mode bits are required

Opcode for Fast Read operations using a dual-input opcode and address, and dual-output data (not supported)

00000b: Not supported

010b: 2 clock cycles of mode bits are required when using a Fast Read instruction with a quad-input opcode and address, and quad-output data

Opcode for Fast Read operations using a quad-input opcode and address, and quad-output data

Maximum time = 2 × (count + 1) × typical erase time

Count = 0

A3:A0 = 0101b

Typical time = (count + 1) × units

1 ms to 32 ms, 16 ms to 512 ms, 128 ms to 4096 ms, 1s to 32s

10:9 units (00b: 1 ms, 01b: 16 ms, 10b: 128 ms, 11b: 1s)

A8:A4 count = 00001b

A10:A9 unit = 16ms = 01b

Typical time = (count + 1) × units

1ms to 32ms, 16 ms to 512 ms, 128 ms to 4096 ms, 1s to 32s

17:16 units (00b: 1 ms, 01b: 16 ms, 10b: 128 ms, 11b: 1s)

A15:A11 count = 00110b

A17:A16 unit = 16 ms = 01b

Typical time = (count + 1) × units

1 ms to 32 ms, 16 ms to 512 ms, 128 ms to 4096 ms, 1s to 32s

24:23 units (00b: 1 ms, 01b: 16 ms, 10b: 128 ms, 11b: 1s)

A22:A18 count = 01001b

A24:A23 unit = 16 ms = 01b

Typical time = (count + 1) × units

1 ms to 32 ms, 16 ms to 512 ms, 128 ms to 4096 ms, 1s to 32s

31:30 units (00b: 1 ms, 01b: 16 ms, 10b: 128 ms, 11b: 1s)

A29:A25 count =18 = 00000b

A31:A30 unit = 1 ms = 00b

Maximum time = 2 × (count + 1) × typical program time

A3:A0 = 0011b

Page size = 2^N bytes

N = 8

A7:A4 = 1000b

Program time = (count + 1) × units

A12:A8 count = 00011b

A13 unit = 64 µs = 1b

Typical time = (count + 1) × units

A17:A14 count = 1110b

A18 = 1 µs = 0b

Typical time = (count + 1) × units

A22:A19 count = 0010b

A23 = 1 µs = 0b

Typical time = (count + 1) × units

16 ms to 512 ms, 256 ms to 8192 ms, 4s to 128s, 64s to 2048s

A28:A24 count = 00100b

A30:A29 units = 4s = 10b

A31 = 1b

xxx0b: May not initiate a new erase anywhere

xxx1b: May not initiate a new erase in the program-suspended page size

xx0xb: May not initiate a new page program anywhere

xx1xb: May not initiate a new page program in program-suspended page size

x0xxb: Refer to the data sheet

x1xxb: May not initiate a read in the program-suspended page size

0xxxb: Additional erase or program restrictions apply

1xxxb: The erase and program restrictions in bits 1:0 are sufficient

xxx0b: May not initiate a new erase anywhere

xxx1b: May not initiate a new erase in the erase-suspended page size

xx0xb: May not initiate a new page program anywhere

xx1xb: May not initiate a new page program in erase-suspended erase type size

x0xxb: Refer to the data sheet

x1xxb: May not initiate a read in the erase-suspended page size

0xxxb: Additional erase or program restrictions apply

1xxxb: The erase and program restrictions in bits 5:4 are sufficient

The device requires this typical amount of time to make progress on the program operation before allowing another suspend.

Program resume-to-suspend interval = (count + 1) × 64 µs

A12:A9 = 7 = 0000b

Maximum time required by the flash device to suspend an in-progress program and be ready to accept another command that accesses the flash array.

Program max latency = (count + 1) × units

Units (00b:128 ns, 01b:1 µs, 10b:8 µs, 11b:64 µs)

A17:A13 = count = 10101b

A19:A18 = 1 µs = 01b

The device requires this typical amount of time to make progress on the erase operation before allowing another suspend.

Erase resume-to-suspend interval = (count + 1) × 64 µs

A23:A20 = 7 = 0111b

Maximum time required by the flash device to suspend an in-progress erase and be ready to accept another command that accesses the flash array.

Erase max latency = (count + 1) × units

Units (00b:128 µs, 01b:1 µs, 10b:8 µs, 11b:64 µs)

A28:A24 = count = 10101b

A30:A29 = 1 µs = 01b

0: Supported

1: Not supported

111101b: Use of legacy polling is supported by reading the status register with the 05h instruction and checking the WIP bit [0] (0 = ready, 1 = busy)

Delay = (count + 1) × unit

A12:A8 = 10011b

A14:A13 units = 01b = 1 µs

FFh: No command required

A23 = 1b

0: Supported

1: Not supported

xxx1b: Issue the FF instruction

1xxxb: Issue the Soft Reset 66/99 sequence

X_xxx1b: Set the IOC bit and then issue instruction 38h

A8 = 0

0: Not supported

1: Supported

xx_xx1xb: If 3-byte address is active, input Fh on DQ0-DQ3 for 8 clocks. If 4-byte address is active, input Fh on DQ0-DQ3 for 10 clocks.

xx_x1xxb: Reserved

xx_1xxxb: Input Fh (mode-bit reset) on DQ0-DQ3 for 8 clocks

x1_xxxxb: Mode bit [7:0]?Axh

1x_xxxxb: Reserved

xxx1b: Mode bits [7:0] = A5h

x1xxb: Mode bit [7:0] = Axh

1xxxb: Reserved

100b: Quad Enable is bit 1 of Status Register 2

0: Feature is not supported

xxx_xxx1b: Nonvolatile Status Register 1; powers up to the last written value; use the 06h instruction to enable writing

xxx_1xxxb: Nonvolatile/Volatile Status Register 1; powers up to the last written value in the non-volatile register

Xx1_xxxxb: Status Register 1 contains a mix of volatile and nonvolatile bits; the 06h instruction is used to enable writing to the register

X1x_xxxxb: Reserved = 1

1xx_xxxxb: Reserved = 1

X1_xxxxb: Reset-enable instruction 66h is issued, followed by the reset instruction 99h

1x_xxxxb: Exit 0-4-4 mode is required prior to other reset sequences

Not supported

Not supported

A21:A14 = 00000000b

A23 and A22 are Reserved bits and are set to 1

Not supported

1xxx_xxxx: Reserved = 1

Support for (1-1-1) FAST_READ command, instruction = 0Ch

Support for (1-1-2) FAST_READ command, instruction = 3Ch

Support for (1-2-2) FAST_READ command, instruction = BCh

Support for (1-1-4) FAST_READ command, instruction = 6Ch

Support for (1-4-4) FAST_READ command, instruction = ECh

Support for (1-1-1) Page Program command, instruction = 12h

Support for (1-1-4) Page Program command, instruction = 34h

Support for Erase Command – Type 1 size, instruction lookup in next Dword

Support for Erase Command – Type 2 size, instruction lookup in next Dword

Support for Erase Command – Type 3 size, instruction lookup in next Dword

Support for Erase Command – Type 4 size, instruction lookup in next Dword

Support for (1-1-1) DTR_Read Command, instruction = 0Eh

Support for (1-2-2) DTR_Read Command, instruction = BEh

Support for (1-4-4) DTR_Read Command, instruction = EEh

Support for volatile individual sector lock Write command, instruction = E1h

Support for nonvolatile individual sector lock read command, instruction = E2h

Support for nonvolatile individual sector lock write command, instruction = E3h

Reserved

H/W HOLD# pin

Deep Power-Down mode

S/W Reset

S/W Reset instruction

Program Suspend/Resume

Unused

Wrap-Around Read mode

Individual Block Lock bit

Individual Block Lock instruction

Individual Block Lock Volatile Protect bit default protect status

Secured OTP

Read Lock

Permanent Lock